Only For Training And Service Purposes - LG KS660 Service Manual

3. TECHNICAL BRIEF
3.20.2. Transmitter : RF block 2 (SGR)
The transmitter takes the modulating symbols sent from baseband and converts them into an RF signal.
It is based on a polar modulator architecture where amplitude and phase modulating are first handled
separately and afterwards merged in the RF-domain. The digital symbol stream enters either a 8PSK or
a GMSK modulator, depending on the desired mode. The GMSK signal is thereby differentially encoded
as postulated by GSM specification 45.004. Signal generation starts with the first completely transmitted
TX Control Register. If any of the generators runs out of symbols, it behaves as if an input series of
repeating dummy symbols would be applied. To simplify mode switch between 8PSK and GMSK, the
two generators are synchronized. On principle, in 8PSK mode the output of the internal 8PSK signal
generator is given in Cartesian (I/Q) coordinates. The desired conversion into polar coordinates
(amplitude and phase) is executed by a CORDIC algorithm. For GMSK mode the CORDIC is not
involved - the incoming GMSK symbols directly determine the modulation frequency of the Sigma-Delta
modulation loop. In the phase path the phase signal is differentiated to obtain a frequency signal, which
is fed into a preemphasis filter to compensate for narrow PLL bandwidth. Afterwards it is applied to the
Sigma-Delta modulation loop. In this way the Sigma-Delta PLL shifts the phase information into RF
domain. The digital amplitude signal is multiplied with the ramping waveform, converted into an analog
voltage and filtered. After that it is mixed with the purely phase modulated RF carrier to gain an
amplitude and phase modulated output signal. The output power can be influenced directly by a PGA
(programmable gain amplifier), if no power control loop is needed, or by specifying a target output level,
if a closed power loop for enhanced output power accuracy is wanted (for details see Chapter 1.6).
Proper transmitter control via the Control Interface is secured in a first step by initialising the chip
according to the RF setup (for example, whether open or closed loop power control is realised). After
that, each burst can be individually programmed. A more detailed introduction is given in Chapter 1.8.
LGE Internal Use Only
< Fig 34. Transmitter Architecture Block Diagram >
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Only for training and service purposes