Toshiba TDP-D1 Service Manual page 99

DMD Interface Considerations
The DDP1000 electronics supports SVGA, XGA and SXGA resolution DDR type DMDs. All
three DMDs can be driven with 1 DDP1000 ASIC. In addition, SXGA can be driven with 2
DDP1000 ASICs for higher performance applications. The DMD interface can be configured to
derive its clock from the DDP1000 master clock (MOSC). In this case the DMD interface clock will
be 50MHz. The DDP1000 electronics also supports supplying an external 60MHz oscillator to run
the DMD interface. See DDP1000 customer datasheet for oscillator requirements. Using an external
60MHz oscillator provides the minimum DMD load time, which results in the best artifact
performance. For XGA systems utilizing a 60MHz DMD clock, line spreading is required on the
input interface to achieve the minimum load time at some pixel clock rates.
Direct RambusTM Memory
The DDP1000 utilizes a high speed Direct RambusTM (RDRAM) memory. To support the
RDRAM a Direct RambusTM clock generator (DRCG) is utilized. This RDRAM interface is a very
high speed and care must be taken in PWB layout to ensure success. While the user can leverage off
of the TI reference design documentation, TI recommends the user follow the RambusTM design
guides called out in the DDP1000 reference design layout guidelines.
RDRAM Memory
The DDP1000 ASIC utilizes a single RDRAM memory.
Direct RambusTM Clock Generator
The DDP1000 ASIC RambusTM interface requires an external Direct RambusTM clock
generator (DRCG).
Flash Memory
The DDP1000 electronics utilizes a Flash memory for storage of ARM software, configuration
and sequences.
98