Aiwa LCX-K170 Service Manual page 20

Compact disc stereo system
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IC, CXD2540Q
Pin No.
Pin Name
1
FOK
2
FSW
3
MON
4
MDP
5
MDS
6
LOCK
7
NC
8
VCOO
9
VCOI
10
TEST
11
PDO
12
VSS
13
PWMI
14
V16M
15
VCTL
16
VPCO
17
VCKI
18
FILO
19
FILI
20
PCO
21
AVSS
22
CLTV
23
AVDD
24
RF
25
BIAS
26
ASYI
27
ASYO
28
ASYE
29
NC
30
PSSL
31
WDCK
32
LRCK
33
VDD
34
DA16
35
DA15
36
DA14
37
DA13
38
DA12
I/O
I
Focus OK input. Used for SENS output and the servo auto sequencer.
O
Spindle motor output filter switching output.
O
Spindle motor on/off control output.
O
Spindle motor servo control.
O
High, when sampled value of GFS at 460Hz is high.
O
Low, when sampled value of GFS at 460Hz is low by 8 times successively.
O
Analog EFM PLL oscillation circuit output.
I
Analog EFM PLL oscillation circuit input. fLOCK=8.6436MHz.
I
TEST pin.
O
Analog EFM PLL charge pump output.
GND.
I
Spindle motor external control input.
O
VCO2 oscillation output for the wide-band EFM PLL.
I
VCO2 control voltage input for the wide-band EFM PLL.
O
Wide-band EFM PLL charge pump output.
I
VCO2 oscillation input for the wide-band EFM PLL.
O
Multiplier PLL (slave=digital PLL) filter output.
I
Multiplier PLL filter input.
O
Multiplier PLL charge pump output.
Analog GND.
I
Multiplier VCO1 control voltage input.
Analog power supply (5V).
I
EFM signal input.
I
Constant current input of the asymmetry circuit.
I
Asymmetry comparator voltage input.
O
EFM full-swing output.
I
Low: asymmetry circuit off; high: asymmetry circuit on.
I
Audio data output mode switching input. Low: serial output; high: parallel output.
O
D/A interface for 48-bit slot. Word clock f=2Fs.
O
D/A interface for 48-bit slot. LR clock f=Fs.
Power supply (5V).
DA16 (MSB) output when PSSL=1.
O
48-bit slot serial data (two's complement, MSB first) when PSSL=0.
O
DA15 output when PSSL=1. 48-bit slot bit clock when PSSL=0.
DA14 output when PSSL=1.
O
64-bit slot serial data (two's complement, LSB first) when PSSL=0.
O
DA13 output when PSSL=1. 64-bit slot bit clock when PSSL=0.
O
DA12 output when PSSL=1. 64-bit slot LR clock when PSSL=0.
28
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