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BD Main 8 Schematic Diagram
( TO AMP/PSU CBA CN201 )
CN7001
JC62D27UG024
TP7001
1
SCLK
AO2_BCK_ADAC
TP7002
2
AO2_LRCK_ADAC
LRCK
TP7003
3
I2S_DATA0
AO2__DATA0_ADAC
TP7004
4
I2S_DATA1
AO2__DATA1_ADAC
TP7005
5
AO2__DATA2_ADAC
I2S_DATA2
TP7006
6
I2S_DATA3
AO2__DATA3_ADAC
7
DGND
TP7008
8
MCLK
AO2_MCLK_ADAC
9
DGND
TP7010
10
PWM,DSP_/RST
/RESET_DSP_PWM
TP7011
11
WIRELESS/RST
/RESET_WSPK
TP7012
12
/INT_WSPK
WIRELESS/INT
TP7013
R7038 0[1005]
13
SCL2
TP7014
R7039 0[1005]
14
SDA2
15
DGND
TP7016
16
CEC
CEC
TP7017
/SYS_RESET
17
XPKRST
TP7018
18
PWM_MUTE
A_MUTE
TP7019
19
RDY
RDY
20
DGND
TP7022
R7044
SUB-TXD
21
TP7024
R7045
SUB-RXD
22
R7046
23
DGND
R7047
TP7020
24
HP MUTE
HP_MUTE
TP7023
R7025
MD
25
TP7025
R7026
26
MC
TP7027
R7027
27
MS1
DGND
( TO BD MAIN 4 )
0.1[F]
0.01[F]
AG
( TO BD MAIN 4 )
R7224
0[1005]
AIN_R
R7225
0[1005]
AIN_L
PON+3V3_BE
PON+5V_BE
( TO BD MAIN 4 )
R7219 0[1005]
( TO BD MAIN 2 )
0
L7201
( TO BD MAIN 2 )
AIN_PDN
G_SCL3
( TO BD MAIN 2 )
G_SDA3
( TO BD MAIN 2 )
( TO BD MAIN 3 )
( TO BD MAIN 2 )
( TO BD MAIN 2 )
( TO BD MAIN 2 )
0[1005]
RXD1
( TO BD MAIN 2 )
0[1005]
TXD1
( TO BD MAIN 2 )
0[1005]
0[1005]
( TO BD MAIN 2 )
0[1005]
SBO-3
( TO BD MAIN 2 )
0[1005]
SBT-3
( TO BD MAIN 2 )
0[1005]
SB3_PIO
( TO BD MAIN 2 )
PON+3V3_BE_ST
C7333
R7218
0[1005]
R7213
0[1005]
C7334
DGND
DGND
AG
C7207
C7204
47/6.3V(WX)
0.1[F]
C7208
C7205
100/6.3V(WX)
0.1[F]
47/6.3V(WX)
C7206
C7209
0.1[F]
DGND
AG
R7217
220[1005]
AG
SYS_RESET
RST
RDY
RDY
SUB-TXD
TX
SUB-RXD
RX
GND
DGND
CVBS_OUT
CVBS_OUT
COMP
( TO BD MAIN 4 )
04-6232-106-102-800
CN7003
DGND
( NO CONNECTION )
1-11-14
IC7201
AK5381ET
R7205
0[1005]
1 AINR
CKS0
16
R7206
0[1005]
2 AINL
CKS2
15
R7207
0[1005]
14
3 CKS1
DIF
13
4 VCOM
PDN
DGND
R7201
33[1005]
12
5 AGND
SCLK
R7202
33[1005]
6
VA
MCLK
11
R7203
33[1005]
7
VD
LRCK
10
R7204
33[1005]
8 DGND
SDTO
9
DGND
C7210
0.1[F]
DGND
TP7204
TP7203
TP7202
TP7201
( TO BD MAIN 7 )
AIN_SCLK
0
AIN_MCLK
L7202
AIN_LRCK
AIN_SDATO
E1T12SCB8
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