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IC Block Diagramm
Port Name
Pin NO.
OSD-BLK1
P139
OSD-CLK
P130
OSD-DATA(3:0) P131.132.135.137.
OSD-VC1
P140
EDO-CAS
P92
EDD-RAS
P94
LDQM
P79
MADDR(20:0)
P96.98-100.102.104-106.
108.110-112.114.116.118.
120-122.124.126.127
MDATA(15:0)
P53.54.56.58-60.62.64.66.
68.70.72-74.76.78
MWE
P82
ROM-CS
P128
SD-CAS
P85
SD-CLK
P84
SD-CS(1:0)
P88.90
SD-RAS
P86
UDQM
P80
DA-BCK
P167
DA-DATA
P161.163.165.
(3:0)
DA-LRCK
P166
DA-XCK
P169
DAI-BCK
P173
DAI-DATA
P171
DAI-LRCK
P172
IEC958
P159
AMADDR
P31-35.37.39.41.
(14:0)
43-46.48.50.51
AMDATA(7:0)
P21-26-28.30
AMOE
P18
AMWE
P20
Type
OSD Interface
I
O
I
I
SDRAM/ROM Interface
O
O
O
O
I/O
O
O
O
O
O
O
O
Audio Interface
O
O
O
I/O
I
I
I
O
Audio SDRAM Interface (Optional)
O
I/O
O
O
- 18 -
Port Description
Black out OSD.
27I 2 or 27 I4 MHz clock.
External OSD color look-up data.
Transparent OSD.
EDO CAS.
EDO RAS.
SDRAM LDQM.
Memory address.
Memory data.
SDRAM/EDO write enable Decoder asserts active LOW
To request a write operation to the SDRAM array
ROM chip select.
Active LOW SDRAM column address.
SDRAM system clock.
Active LOW SDRAM bank select.
Active LOW SDRAM row address.
SDRAM UDQM.
PGM bit clock. Divided by 8 from DA-XCK can be either
48 or 32 times the sampling clock.
PCM data our, six channels. Serial audio samples relati-
ve to DA-BCK clock. Resulting in downmixed audio
output.
PCM left-right clock. ldentifies the channel for each audio
sample. The polarity is programmable.
Audio external frequency clock. Used to generate DA-
BCK and DA-LRCK. DA-XCK can be either 384 or 256
times The sampling frequency.
PCM input bit clock.
PCM input data, two channels. Serial audio samples
relative to DA-BCK clock, resulting downmixed audio
output
PCM input left-right clock.
Bitstream or PCM data out in IEC-958 format.
Audio SDRAM address bus.
Audio SDRAM data bus.
Audio SDRAM output enable.
Audio SDRAM write enable.
IC Block diagram
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