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IC Block Diagramm
Port Name
Pin NO.
AREQUEST
P194
ADACK
P198
DVD-DATA
P186-189
(7:4)
DVD-DATA3/
P185
CD-C2P0
DVD-DATA2/
P184
CD-BCK
DVD-DATA1/
P182
CD-LRCK
DVD-DATA0/
P180
CD-DATA
ERROR
P200
VDACK
P196
VREQUEST
P191
VSTROBE
P192
HSYNC
P157
VCLK
P177
VDATA(7:0)
P142.143.145.148
150.152.154.155
VSYNC
P158
Type
Parallel DVD/CD or Serial CD Interface
O
I
I
I
I
I
I
I
I
O
I
Video Output
I/O
I
O
I/O
Port Description
Audio request. Decoder asserts AREQUEST to indicate
that the audio input buffer has available space.
Audio data acknowledge.
DVD parallel compressed data from DVD DSP. When
DVD DSP sends 32-bit words. It must write the MSB first
Asserted HIGH indicates a corrupted byte. Decoder
keeps The previous valid picture on-screen until the next
valid Picture is decoded. This pin is shared with DVD
Compressed data DVD-DATA3.
CD bit clock. Decoder accept multiple BCK rates. This pin
Is shared with DVD compressed data DVD-DATA2.
Programmable polarity 16-bit word synchronization to the
Decoder (right channel HIGH). This pin is shared with
DVD compressed data DVD-DATA1)
Serial CD data. This pin is shared with DVD compressed
Data DVD-DATA0
Error in input data. If ERROR signal is not available from
The DSP it must be grounded through a 4.7K resistor.
Video data acknowledge. Asserted when DVD data is
valid. Polarity is programmable.
Video request. Decoder asserts REQUEST to indicate
that The video input buffer has available space. Polarity
is Programmable
Video strobe. Programmable dual mode pulse.
Asynchronous and synchronous. In Asynchronous mode,
an external source pulses VSTROBE to indicate data is
ready for transfer. In synchronous mode VSTROBE
clocks data.
Horizontal sync. The decoder begins outputting pixel
data for a new horizontal line after the falling (active)
edge of HSYNC.
Video clock. Clocks out data on input. VDATA(7:0).
Clock is typically 27 MHz.
Video data bus. Byte serial CbYCrY data synchronous
With VCLK. At power-up, the decoder initially drives
VDATA. Any other device attached to the video bus must
be 3-stated when the decoder is powered-up. During
Boot-up, the decoder initializes to 3-state VDATA: but
For a brief period it drives VDATA.
Vertical sync. Bi-directional, the decoder outputs the top
Border of a new field on the first HSYNC after the
falling Edge of VSYNC. VSYNC can accept vertical
synchronization or top/bottom field notification from an
external source. (VSYNC HIGH = bottom field. VSYNC
LOW = Top field)
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IC Block diagram
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