Blaupunkt DVP 01 Service Manual page 16

IC Block Diagramm
ZiVA-3CR IC COM PORT
Port Name Pin NO.
RESET P13
SYSCLK P178
PIO(10:0) P190.174.156.153.14.7.
141.138.133.129.52.1
A-VDD P176
A-VSS P179
VDD P5.12.17.27.36.40.47.
55.61.65.69.75.81.87.
91.95.101.107.113.
117.123134.144.149
160.168.181.193.197
VSS P7.14.19.29.38. 42. 49.
57.63.67. 71.77. 83.
89.93.97.103.109. 115.
119.125.136.146. 151.
162.170.183.195.199
CS P206
DTACKSEL P189
HADDR(2:0) P202-204
HDATA(7:0) P2-4,6,8-11
HOST8SEL P201
INT P16
RD P208
R/W P207
WAIT/DTACK P15
Type
System services
I Hardware reset. An external device asserts RESET
(active LOW) to execute a decoder hardware reset. TO
ensure proper initialization after power stable, assert
RESET for at least 20 us.
I System clock, Decoder requires an external 27 MHz TTL
Oscillator. Drive with the same 27-MHz as VCK.
I/O Programmable I/O pins.
Power and Ground
Analog 3.3-V analog supply voltage.
Power
Analog Analog ground for PLL
Ground
Power 3.3-V supply voltage for core logic and I/O Signals.
Ground Ground for core logic and I/O signals.
8-bit Host Interface
I Host chip select. Host asserts CS select the decoder for
a read or write operation. The falling edge of this signal
Triggers the read or write operation.
I Tie HIGH to select WAIT signal, LOW to select DTACK
Signal (Motorola 68k mode).
I Host address bus 3-bit address bus selects one of eight
Host interface registers.
I/O 8-bit bi-directional host data bus. Host writes data to the
Decoder Code FIFO via HDATA (7:0). MSB of the
32-bit word is written first. The host also reads and
writes the decoder internal registers and local SDRAM/
ROM via HDATA(7:0).
I Drive HIGH to Select 8-bit, LOW to select 16-bit host
16-bit host interface.
0,0D, Host interrupt. Open drain signal, must be pulled-up to
PU 3.3 volts.
I Read strobe in I mode. Must be held HIGH in M Mode
I Read/write strobe in M mode. Write strobe in I mode.
Host asserts R/W LOW to select write and LOW to
Select Read.
0.0D. Transfer not complete / data acknowledge. Active LOW
PU To indicate host initiated transfer is not complete. WATT
Is asserted after the falling edge of CS and reasserted
When decoder is ready to complete transfer cycle.
Open drain signal. Must be pulled-up to 3.3 volts.
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IC Block diagram
Port Description