Beko E1 CHASSIS Service Manual page 12

7. IC DATASHEETS&SPECS
TDA 9345
GENERAL DESCRIPTION
The various versions of the TDA9345 and TDA9345 PS-N3 combine the functions of a video processor
together with a µ-Controller, a Teletext decoder and US Closed Caption decoder. The Teletext decoder
has an internal RAM memory for 1 page(TDA 9345) or 10 page(TDA 9346) text. The ICs are intended
to be used in economy television receivers with picture tubes up to 100°. The ICs have supply voltages
of 8 V and 3.3 V and they are mounted in an SDIP-64 envelope. The features are given in the following
feature list.
FEATURES
a) TV processor
• Multi-standard vision IF circuit with alignment-
free PLL demodulator
• Internal (switchable) time-constant for the IF-
AGC circuit
• The mono intercarrier sound circuit has a
selective FM-PLL demodulator which can be
switched to the different FM sound frequencies
(4.5/5.5/6.0/6.5 MHz). The quality of this system
is such that the external band-pass filters can
be omitted.
• Source selection between the 'internal' CVBS
and an external CVBS or Y/C signal
• Integrated chrominance trap circuit
• Integrated
luminance
adjustable delay time
• Picture improvement features with peaking
(with switchable centre frequency, depeaking,
variable positive/negative overshoot ratio and
video dependent coring) and blue- and black
stretching. All features are available for CVBS,
Y/C and YPBPR signals.
• Integrated
chroma
switchable centre frequency
• Only one reference (12 MHz) crystal required
for the µ-Controller, and the colour decoder
• Multi-standard colour decoder with automatic
search system
• Internal base-band delay line
• Indication of the Signal-to-Noise ratio of the
incoming CVBS signal
• A linear RGB/YUV/YPBPR input with fast
blanking for external RGB/YUV sources. The
synchronisation circuit can be connected to the
incoming Y signal. The OSD signals are
internally supplied
decoder.
delay line
band-pass filter
µ-Controller
from the
• RGB control circuit with 'Continuous Cathode
Calibration', white point and black level off-set
adjustment so that the colour temperature of the
dark and the light parts of the screen can be
chosen independently.
• OSD/Text gain reduction control
• Horizontal synchronization with two control
loops and alignment-free horizontal oscillator
• Vertical count-down circuit
• Vertical driver optimized for DC-coupled
vertical output stages
• Low-power start-up of the horizontal drive
circuit
• Macrovision keying possibility for horizontal
synchronisation.
with
b) µ-Controller
• 80C51 µ-controller core standard instruction
set and timing
• 1 µs machine cycle
• 32 - 64Kx8-bit(TDA9345) or 64-128Kx8-
bit(TDA9346) late programmed ROM
• 3Kx8(TDA9345)
with
Auxiliary RAM (shared with Display)
• Interrupt
enable/disable with two level priority
• Two 16-bit Timer/Counter registers
• One 16-bit Timer with 8-bit Pre-scaler
• WatchDog timer
• Auxiliary RAM page pointer)
• 16-bit Data pointer
• Stand-by, Idle and Power Down modes
• 14 bits PWM for Voltage Synthesis Tuning
• 8-bit A/D converter
• 4 pins which can be programmed as general
I/O pin, ADC input or PWM (6-bit) output
11
or 12Kx8(TDA9346)-bit
controller for individual