Keithley 3930A Service Manual page 25

SECTION2
Principles
of
Operation
2.4 SYNTHESIZER OPERATING
PRINCIPLES
The Model 3930A uses a digital direct type of synthesizer.
This configuration yields more accurate, stable
waveforms than is possible with conventional oscillators.
Figure 2-3 shows a simplified block diagram of the digital
synthesizer address generator. The address generator is
made up of a clock register, a binary adder, and the fre-
quency setting register. The clock register counts clock
pulses, and the frequency setting register stores fre-
quency setting information. The binary adder adds the
outputs of the clock register and the frequency setting
register.
Initially, the frequency setting register is programmed
with the binary value representing the programmed op-
erating frequency, and the clock register is cleared (set to
all OS). The clock register counts clock
pulses,
and the ad-
dress output increases value with time until the register
overflows, at which point the register value returns to all
OS. The cycle starts again, and a ramp waveform shown in
Figure Z-4 is generated. The slope of the ramp is directly
proportional to the programmed frequency, and the
repetition rate is inversely proportional to the set fre-
quency.
used.
The address output of the clock register is then applied to
memory in which waveform data is stored, as shown in
Figure 2-5. The output of the waveform memory is ap-
plied to the D/A converter, which converts the digital
waveform data to an analog waveform.
In the Model 393OA, the clock and frequency setting reg-
isters are both 36 bits wide. The clock has a frequency
resolution of 2% x WHz. As a result, the minimum fre-
quency setting (when 0 . . . 0012 is loaded into the fre-
quency setting register) is 2% x lo-' / 2% = O.lmHz. Note
that the address output uses the most significant 12 bits
out of the 36 bits available, and a Q-bit D/A converter is
(ConstafEZquency)
I
> Address Output to Memory
)
Clock Register
Binary Adder
?
Frequency Register
A
Frequency Setting Data
Fipre 23.
Frequency Synthesizer Address Generator Diagram
2-s