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Summary of Contents for Oxford Semiconductor EV-TD122-UHC124-PCI
- Page 1 UG-0037 Nov 06 EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide Oxford Semiconductor, Inc. 1768 McCandless Drive Milpitas, CA 95035 USA http://www.oxsemi.com...
- Page 2 EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide Oxford Semiconductor, Inc. ON Semiconductor is a register trademark of Semiconductor Components Industries, LLC. PLX is a registered trademark of PLX Technology. All other trademarks are the property of their respective owners. © Oxford Semiconductor, Inc. 2006 The content of this manual is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Oxford Semiconductor, Inc. Oxford Semiconductor, Inc. assumes no responsibility or liability for any errors or inaccuracies that may appear in this book. External—Free Release UG-0037 Nov 06...
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Page 3: Table Of Contents
........vi Chapter 1 - EV-TD122-UHC124-PCI ..............1-1 Overview . - Page 4 Contents EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide This page is intentionally blank External—Free Release UG-0037 Nov 06...
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Page 5: Preface
Preface This manual documents the EV‐TD122‐UHC124‐PCI Evaluation Board hardware. Revision Table I documents the revisions of this manual Information Table I Revision Information Revision Modification Nov 2006 First publication Typographic In this manual, the conventions listed in Table II apply. Conventions Table II Typographic Conventions Convention Meaning Italic Letters With Initial Capital Letters A cross-reference to another publication Software code, or text typed in via a keyboard Courier Font 1, 2, 3 A numbered list where the order of list items is significant... -
Page 6: Contacting Oxford Semiconductor
EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide Contacting See the Oxford Semiconductor website (http://www.oxsemi.com) for Oxford Semi- further details about Oxford Semiconductor devices, or email sales@oxsemi.com. conductor External—Free Release UG-0037 Nov 06... -
Page 7: Chapter 1 - Ev-Td122-Uhc124-Pci
Chapter 1 EV-TD122-UHC124-PCI Overview The EV‐TD122‐UHC124‐PCI Evaluation Board is a system for TD122 and UHC124 customer evaluations and internal software development in the PC environment. The EV‐TD122‐UHC124‐PCI Evaluation Board allows the user to install and use the TD122 or UHC124 in any PCI‐based computer. Application software running on the system has access to the TD122 or UHC124 via the PCI memory space.The EV‐TD122‐UHC124 board can be used without the PCI Bridge Board, the PCI104. The EV‐TD122‐UHC124‐PCI allows customers to: Evaluate the Oxford Semiconductor TD122 and UHC124 USB host controller Run TD122 and UHC124 demonstrations Develop user software for TD122‐UHC124‐based applications While the EV‐TD122‐UHC124‐PCI can be used to evaluate the TD122‐UHC124, it will not result in optimal performance due to the long access times of the PCI bus. For optimal performance evaluation, the TD122‐UHC124 should be placed directly on the system bus using the EV‐TD122‐UHC124 board as described in Chapter 2 . The EV‐TD122‐UHC124‐PCI Evaluation Board is a two‐board combination of the following: An EV‐TD122‐UHC124 Evaluation Board with 2 or 4 USB host ports A 33 MHz, 32‐bit PCI Bridge Board, the PCI104 The EV‐TD122‐UHC124 Evaluation Board contains the TD122 or the UHC124 and all the USB‐specific hardware. UG-0037 Nov 06 External—Free Release 1—1... -
Page 8: Pci Operation
EV-TD122-UHC124-PCI EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide The PCI104 Bridge Board contains the PCI9030 PCI bridge chip that bridges the PCI bus to the TD122 or UHC124. Power and control signals to the PCI bus are maintained by the PCI bridge chip, while initialization and configuration of the PCI bridge chip is maintained by the on‐board serial EEPROM. Figure 1‐1 illustrates the orientation of the two boards. The combined boards are approximately one inch thick and require space for two PCI devices, but only one PCI slot. The two or four host USB connectors are easily accessible through the openings in the computer case. Chapter 2 describes the EV‐TD122‐UHC124 Evaluation Board. Chapter 3 describes the PCI104 Bridge Board. For complete information about the TD122 device, see the TD122 USB Host Controller Technical Manual. For complete information about the UHC124 device, see the UHC124 USB Host Controller Data Sheet. Figure 1-1 EV-TD122-UHC124-PCI System Board Orientation PC104 Connectors EV-TD122-UHC124 PCI Connector PCI104 PCI Slot CPU Motherboard Every PCI implementation has a PCI configuration space, where the PCI configuration registers are found. PCI configuration registers are ... - Page 9 EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide EV-TD122-UHC124-PCI Table 1-1 Standard PCI Configuration Register Space Byte 3 Byte 2 Byte 1 Byte 0 Offset BIST Header Type Latency Timer Cache Line Size Base Address Register 0 (BAR 0) Base Address Register 1 (BAR 1)
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Page 10: Configuration
EV-TD122-UHC124-PCI EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide Configuration The EV‐TD122‐UHC124‐PCI has two memory mapped register spaces and one I/O mapped register space. The address locations of the various spaces are determined by the Base Address Registers of the PCI configuration registers. Base Address Register 0 (BAR0) of the PCI configuration registers contains the address of the memory mapped PCI bridge controller registers. BAR1 contains the I/O address for the same PCI bridge controller registers. The PCI bridge controller registers are mapped into both memory and I/O space, so that these registers can be accessed via memory accesses or I/O addressing. BAR3 contains the address of the memory mapped TD122 or UHC124 registers. Figure 1‐2 illustrates the register mappings within a PCI system. Figure 1-2 PCI104 Register Mappings Configuration Registers PCI9030 Offset Register 0x10 BAR0 (mem) 0x14 BAR1 (I/O) 0x18 BAR2 (mem) 0x1C... - Page 11 EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide EV-TD122-UHC124-PCI Table 1-3 Serial EEPROM Registers Serial EEPROM Offset Description Default PCI Device ID 012Fh PCI Vendor ID 192Eh PCI Status Register 0290h PCI Command Register 0003h PCI Class Code 0680h PCI Class Code / Revision Number...
- Page 12 EV-TD122-UHC124-PCI EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide Table 1-3 Serial EEPROM Registers Serial EEPROM Offset Description Default MSW of Expansion ROM Local Base Address (Remap) 0010h LSW of Expansion ROM Local Base Address (Remap) 0000h MSW of Local Address Space 0 Bus Region Descriptor...
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Page 13: Chapter 2 - Ev-Td122-Uhc124 Evaluation Board
Chapter 2 EV-TD122-UHC124 Evaluation Board Overview This chapter describes the hardware operation and configuration options available for the EV‐TD122‐UHC124 in stand‐alone mode. These options allow customers to directly connect the TD122 or the UHC124 to their embedded processor or CPU without going through a PCI bus. The use of this board without the PCI bridge card increases performance and allows driver development in real‐world applications of the product. Figure 2‐1 shows the EV‐TD122‐UHC124 block diagram. UG-0037 Nov 06 External—Free Release 2—1... -
Page 14: Board Operation Requirement
EV-TD122-UHC124 Evaluation Board EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide Figure 2-1 EV-TD122-UHC124 Block Diagram 5.0 V to 3.3 V DC Converter Resistors 3.3 V 3.3 V PCI 3.3 V Converter Mictor Test Headers (Optional) Port 1 Processor Type A... -
Page 15: Default Configurations
EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide EV-TD122-UHC124 Evaluation Board Default The following factory default settings support the development of the Configura- TD122 USB host for Port 1 and Port 2: tions R54, R55 (0_1206 Ω) populated to route 5 V from the PCI104 connectors R49 (0_1206 Ω) populated for 3.3 V from the voltage regulator R23, R29, R31, R33 (0 Ω) populated for non‐multiplex mode (MODE = 1) R26 (4.7 kΩ) populated for non‐multiplex mode (MODE = 1) R38 (0 Ω) populated for /ADS signal inversion R5, R9 (4.7 kΩ) populated when the TD122 is installed R35, R52, R14, R41 (4.7 kΩ) populated for control signals pull‐ups U1, U3, U5, U7 (with an STF201‐30) populated for ESD protection, series resistance, and pull‐downs to match impedance Optional If the UHC124 is installed in U10, R6 and R8 (4.7 kΩ) are installed as Configura- pull‐ups. This allows all four standard‐A ports to be used. tions To use the EV‐TD122‐UHC124 in multiplex mode (MODE = 0): Install a 0 Ω resistor in R24, R28, R32, R34. Remove the 0 Ω resistor from R23, R29, R31, R33. Install R27 (4.7 kΩ) and remove R26. If the ADS input signal is already active high and does not need to be inverted, install R36 (0 Ω) and remove R38. To use 3.3 V from the PCI connector, install R47 (0_1206 Ω) and remove R49. To use a different ESD protection part, USBDF01W5, install U2, U4, U6, ... -
Page 16: Reset
EV-TD122-UHC124 Evaluation Board EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide 3.3 V Power Supply The EV‐TD122‐UHC124 3.3 V power is supplied by one of three sources: From U12, a 5 V‐to‐3.3 V DC converter (default setting). From the PC104 connector. Install R47 (0_1206 Ω) and remove R49. From an external power supply connected to the test pin on JP7.3. Protection circuitry is not provided (remove R47 and R49). Reset The /RESET pin of the TD122 or UHC124 is connected to the PC104 connector. Users can control /RESET through a CPU GPIO. Each of the D pairs has a 2‐pin, 0.1 inch spacing, connector to support attachment of a differential probe (JP1‐JP4) Signals These traces are impedance controlled to 90 Ω + 10% LEDs The EV‐TD122‐UHC124 has the following LEDs to enable monitoring of the normal operation of the board: D1‐D4: Type A VBUS Power Indicator D5: 3.3 V Power Rail Indicator D6: 5 V Power Rail Indicator Oscillator Use of a 6 MHz crystal, instead of a crystal oscillator, is recommended to lower EMI. The only footprint provided in the EV‐TD122‐UHC124 board Input uses a 6 MHz crystal located at Y1 (Ecliptek Corp., E2SAA18‐6.000M, 18 pF internal load). - Page 17 Chapter 3 PCI104 Bridge Board Overview The PCI104 contains a PLX Technology PCI9030 bridge chip, an Atmel AT93C66A‐10PI‐2.7, a ROM socket, and three connectors. The PCI104 board bridges between the PCI bus and the TD122‐UHC124 local bus. The local bus is routed out to the standard PC104 connectors (J1 and J2). The EV‐TD122‐UHC124 interfaces to the PCI104 Bridge Card via these three female connectors. Another proprietary, non‐PC104 connector (J3) was added to support a 32‐bit interface and additional signals not included in the PC104 signal definition. Figure 3‐1 shows the PCI104 block diagram. UG-0037 Nov 06 External—Free Release 3—1...
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Page 18: Chapter 3 - Pci104 Bridge Board
PCI104 Bridge Board EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide Figure 3-1 PCI104 Bridge Board 5.0 V to 3.3 V Converter 3.3 V PCI_3.3 V PCI Bus Local Bus PCI9030 PQFP176 EEPROM The PCI104 board uses the PCI9030 bridge device. The PCI configuration registers are stored in an on‐board EEPROM. Power The PCI104 board gets its 5 V power from the standard PCI bus edge Distribution connector (U2 – eight 5 V pins). The 5 V supply is routed directly to the EV‐TD122 via the PC104 connectors (J1.D16, J2.B3, J2.B29). The PCI104 board 3.3 V power is supplied by one of two sources: ... -
Page 19: Local Bus Configuration
EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide PCI104 Bridge Board Local Bus The PCI9030 local bus is connected directly to the EV‐TD122‐UHC124 Configuration board via the PC104 connectors. Refer to the PCI9030 Data Book for a detailed explanation of its operation. PCI9030 CS1L chip select is routed to the EV‐TD122‐UHC124. Register Space 1 of the PCI9030 controls CS1L. The number values programmed into Space 1 registers of the EEPROM are shown below. Changing values in the EEPROM requires an application from PLX operating across the PCI bus. Space 1 has 8‐bit local and PCI space and contains 4 Kb memory space size. There is no prefetch on space 1. Space 1 Range 0xFFFF_F000 Space 1 Remap 0x0000_0001 Space 1 Descriptor 0x4013_F940 Space 1 Base Address 0x0000_0801 Space 1 Initialization Control 0x0030_0041 The local timing is five WAIT states for READs (address‐to‐data) and seven for WRITEs (address‐to‐data) to make the PCI104 backwards compatible with previous Oxford Semiconductor chips. The other WAIT states are: three RD (data‐to‐data), three RD/WR (data‐to‐address), one WR (data‐to‐data), and one WR cycle hold. An optimum bus access will not create a significant increase in performance in the EV‐TD122‐ UHC124‐PCI system. For better performance evaluation, the TD122 and UHC124 should be embedded directly on the system bus using the ... - Page 20 PCI104 Bridge Board EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide This page is intentionally blank 3—4 External—Free Release UG-0037 Nov 06...
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Page 21: Chapter 4 - Schematics
Chapter 4 Schematics Overview This chapter provides the EV‐TD122‐UHC124 and PCI104 schematics. The term “EVB12X” refers to the EC‐TD122‐UHC124 board. U10 is shown as a “TD12X”, which refers to either the TD122 or UHC124 USB chip, depending on the installation. UG-0037 Nov 06 External—Free Release 4—1... - Page 22 Schematics EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide Figure 4-1 EV-TD122-UHC124 Top-Level Schematic 4—2 External—Free Release UG-0037 Nov 06...
- Page 23 EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide Schematics Figure 4-2 EV-TD122-UHC124 Test Headers UG-0037 Nov 06 External—Free Release 4—3...
- Page 24 Schematics EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide Figure 4-3 EV-TD122-UHC124 PC104 Connector 4—4 External—Free Release UG-0037 Nov 06...
- Page 25 EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide Schematics Figure 4-4 EV-TD122-UHC124 - TD12X and USB Ports Schematic UG-0037 Nov 06 External—Free Release 4—5...
- Page 26 Schematics EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide Figure 4-5 PCI104 Top-Level Schematic 4—6 External—Free Release UG-0037 Nov 06...
- Page 27 EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide Schematics Figure 4-6 PCI104 PCI Connector UG-0037 Nov 06 External—Free Release 4—7...
- Page 28 Schematics EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide Figure 4-7 PCI9030 Bridge Chip 4—8 External—Free Release UG-0037 Nov 06...
- Page 29 EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide Schematics Figure 4-8 PC104 Connectors UG-0037 Nov 06 External—Free Release 4—9...
- Page 30 Schematics EV-TD122-UHC124-PCI and EV-TD122-UHC124 Evaluation Board User Guide Figure 4-9 PC104 Expansion ROM 4—10 External—Free Release UG-0037 Nov 06...
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