Summary of Contents for Oxford Semiconductor EV-OXU200-PCI
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UG-0038 Mar 07 EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Oxford Semiconductor, Inc. 1900 McCarthy Boulevard, Suite 210 Milpitas, CA 95035 http://www.oxsemi.com...
Preface This manual documents the EV‐OXU200‐PCI and EV‐OXU200 Evaluation Board hardware. Revision Table I documents the revisions of this manual Information Table I Revision Information Revision Modification Feb 2007 First publication Mar 2007 Added the Certified USB logo to the cover page Typographic In this manual, the conventions listed in Table II apply. Conventions Table II Typographic Conventions Convention Meaning Italic Letters With Initial Capital Letters A cross-reference to another publication Software code, or text typed in via a keyboard Courier Font...
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EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide This page is intentionally blank External—Free Release UG-0038 Mar 07...
Chapter 1 EV-OXU200-PCI Overview The EV‐OXU200‐PCI Evaluation Board is a system for OXU200 customer evaluations and internal software development in the PC environment. The EV‐OXU200‐PCI Evaluation Board allows the user to install and use the EV‐OXU200 in any PCI‐based computer. Application software running on the system has access to the OXU200 via the PCI memory space. The EV‐OXU200‐PCI Evaluation Board is a two‐board combination of the following: An EV‐OXU200 Evaluation Board A 33 MHz, 32‐bit PCI Bridge Board, the PCI104 The EV‐OXU200 Evaluation Board contains the OXU200 and all the USB‐specific hardware. The PCI104 Bridge Board contains a PCI‐to‐local‐bus bridge chip that bridges the PCI bus to the OXU200. Power and control signals to the PCI bus are maintained by the PCI bridge chip, while initialization and configuration of the PCI bridge chip is maintained by the on‐board serial EEPROM. Figure 1‐1 illustrates the orientation of the two boards. The combined boards are approximately one inch thick and require space for two PCI devices, but only one PCI slot. The OXU200 peripheral USB connector is accessible through the opening in the computer case. Chapter 2 describes the EV‐OXU200 Evaluation Board. Chapter 3 describes the PCI104 Bridge Board. For complete information about the OXU200 device, see the OXU200 Hardware Reference Manual. UG-0038 Mar 07 External—Free Release 1—1...
EV-OXU200-PCI EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Figure 1-1 EV-OXU200-PCI System Board Orientation PC104 Connectors EV - OXU200 PCI Connector PCI104 PCI Slot CPU Motherboard Every PCI implementation has a PCI configuration space, where the PCI Operation configuration registers are found. PCI configuration registers are accessed with read/write to configuration space, which is separate from memory and I/O space. Table 1‐1 lists the standard PCI configuration register space for all PCI functions on the PCI bus. Table 1-1 Standard PCI Configuration Register Space Byte 3...
EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide EV-OXU200-PCI The PCI104 can be identified on the PCI bus during enumeration by the following PCI configuration registers: Table 1-2 PCI Configuration Registers Register Power-On Value Vendor ID 192Eh Device ID 016Bh Revision 0001h Class Code 0680h Subsystem ID 016Bh Subsystem Vendor ID 192Eh Most operating systems provide functions for finding devices on the PCI bus. These functions typically key off the Vendor and Device IDs, or the Class Code. Because the Class Code for the PCI104 appears as a PCI Bridge with sub class code “other”, the search should be keyed to the ...
EV-OXU200-PCI EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Figure 1-2 PCI104 Register Mappings Configuration Registers PCI9030 Offset Register 0x10 BAR0 (mem) 0x14 BAR1 (I/O) 0x18 BAR2 (mem) 0x1C BAR3 (mem) 0x20 BAR4 (mem) 0x24 BAR5 (mem) Local Addr Space 0...
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EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide EV-OXU200-PCI Table 1-3 Serial EEPROM Registers Serial EEPROM Offset Description Default (Maximum Latency and Minimum Grant are not loadable) 0000h Interrupt Pin (Interrupt Line Routing is not loadable) 0100h MSW of Power Management Capabilities...
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EV-OXU200-PCI EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Table 1-3 Serial EEPROM Registers Serial EEPROM Offset Description Default MSW of Expansion ROM Bus Region Descriptor 0000h LSW of Expansion ROM Bus Region Descriptor 0000h MSW of Chip Select 0 Base Address...
Chapter 2 EV-OXU200 Evaluation Board Overview This chapter describes the hardware operation and configuration options available for the EV‐OXU200 in stand‐alone mode. These options allow customers to directly connect the OXU200 to their embedded processor or CPU without going through a PCI bus. The use of this board without the PCI bridge card increases performance and allows driver development in real‐world applications of the product. Figure 2‐1 shows the EV‐OXU200 block diagram. Figure 2-1 EV-OXU200 Block Diagram 5.0 V to 3.3 V 3.3 V Converter Resistors 1.8 V to 3.3 V I/O 1.8 V Mictor Test Headers REGOUT (Optional) Processor OXU200 BGA64 or...
EV-OXU200 Evaluation Board EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Board The EV‐OXU200 requires a DC power source capable of supplying 5 V ± 10% at 1.0 A through a power switch. Operation Requirement Default Zero‐Ohm resistors are used to set the following factory default Configura- configurations: tions R1, R3 (0 Ω) populated to route 5 V from the PC104 connectors R30, R31 (0 Ω) populated, R29 (0 Ω) removed to use on‐board 12 MHz crystal R28 (0 Ω) populated, R27 (0 Ω) removed to set V to 3.3 V I/O Power In the default mode, the EV‐OXU200 receives all its power from the 5 V Distribution pins of the PC104 connector. The 5 V supply drives the 3.3 V DC regulator. Alternative power‐supply options are described below. The power for the core voltage (V pins) comes from the OXU200’s DD1.8 internal regulator. This regulator can also be selected to drive the 1.8 V I/O option for V 5 V Power Supply The EV‐OXU200 5 V power is supplied by one of two sources: ...
EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide EV-OXU200 Evaluation Board 3.3/1.8 V V Wide Range I/O Power Supply The EV‐OXU200 provides either 1.8 V or 3.3 V for V , the wide range power. The voltage is selected through the intallation or removal of resistors as described below. While the OXU200 allows any voltage in this range, any other value is customer specific and is not directly supported by this evaluation board. The EV‐OXU200 V power is supplied by one of two sources: From the 3.3 V power rail (default setting). Install R28 (0 Ω) and remove R27 (0 Ω). From the OXU200’s 1.8 V internal regulator. Install R27 (0 Ω) and remove R28 (0 Ω). Oscillator The EV‐OXU200 uses a 12 MHz crystal at Y1 for the OXU200 /OSC clock source. Input A 12 MHz oscillator can be soldered at the U6/U7 dual‐footprint by the customer and used as the OXU200 clock source. To enable this mode, install R29 (0 Ω) and remove R31 (0 Ω). Also, remove R30 (0 Ω)because the OSC pin must be floating in this configuration. Below are the ...
EV-OXU200 Evaluation Board EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Over- Besides the ESD transient protection provided by the external ESD devices, the OXU200 V pin is also protected against steady‐state Voltage voltages above 5.1 V (typical) by the voltage divider resistor (R32 = 390 Ω) and the Zener diode D2. When the OXU200 is connected to a host, the Protection Zener diode protects the OXU200 from damage. ® Zener diode: ON Semiconductor BZX84C5V1LT1G, 225 mW, 5.1 V breakdown LEDs The EV‐OXU200 has the following LEDs to enable monitoring of the normal operation of the board: D5: 1.8 V Power Rail Indicator D3: 3.3 V Power Rail Indicator D4: 5.0 V Power Rail Indicator D1: Peripheral Port V Power Indicator Mounting The EV‐OXU200 board has four un‐plated standoff holes, one near each corner of the board. Each hole is 0.146 inch in diameter. The placement Holes matches the PCI104 PCI board which together make the EV‐OXU200‐ PCI. Test Points The following test points are furnished on the EV‐OXU200: ...
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Chapter 3 PCI104 Bridge Board Overview The PCI104 Bridge Board, measured at 5.55 in. (140.9 mm) by 3.00 in. (76.2 mm), can be employed to: Evaluate the Oxford Semiconductor OXU200 USB peripheral controller Run OXU200 demonstrations Develop user software for OXU200‐based applications Serve as a subassembly in an OEM product to provide USB OTG and host controller functionality While the EV‐OXU200‐PCI can be used to evaluate the OXU200, it will not result in optimal performance due to the long access times of the PCI bus. For optimal performance evaluation, the OXU200 should be placed directly on the system bus using the EV‐OXU200 board as described in Chapter 2 . The PCI104 board bridges between the PCI bus and the OXU200 local bus. The local bus is routed out to the standard PC104 connectors (J1 and J2). The EV‐OXU200 interfaces to the PCI104 Bridge Card via these three female connectors. Another proprietary, non‐PC104 connector (J3) was added to support a 32‐bit interface and additional signals not included in the PC104 signal definition. Figure 3‐1 shows the PCI104 block diagram. UG-0038 Mar 07 External—Free Release 3—1...
PCI104 Bridge Board EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Figure 3-1 PCI104 Bridge Board 5.0 V to 3.3 V Converter 3.3 V PCI_3.3 V PCI Bus Local Bus PCI9030 PQFP176 EEPROM The PCI104 board uses the PCI9030 bridge device. The PCI configuration registers are stored in an on‐board EEPROM. Power The PCI104 board receives its 5 V power from the standard PCI bus edge connector (U2 – eight 5 V pins). The 5 V supply is routed directly to the Distribution EV‐OXU200 via the PC104 connectors (J1.D16, J2.B3, J2.B29). The PCI104 board 3.3 V power is supplied by one of two sources: ...
EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide PCI104 Bridge Board Local Bus The PCI9030 local bus is connected directly to the EV‐OXU200 board via the PC104 connectors. Refer to the PCI9030 Data Book for a detailed Configuration explanation of its operation. PCI9030 CS1L chip select is routed to the EV‐OXU200. Register Space 1 of the PCI9030 controls CS1L. The number values programmed into Space 1 registers of the EEPROM are shown below. Changing values in the EEPROM requires an application from PLX operating across the PCI bus. Space 1 has 16‐bit local and PCI space and contains 32 Kb memory space size. There is no prefetch on space 1. Space 1 Range 0xFFFF_8000 Space 1 Remap 0x0000_0001 Space 1 Descriptor 0x4040_A040 Space 1 Base Address 0x0000_4001 Space 1 Initialization Control 0x0024_9864 The local timing is one WAIT state for READs (address‐to‐data) and one for WRITEs (address‐to‐data) to make the PCI104 backwards compatible with previous Oxford Semiconductor chips. The other WAIT states are: zero RD (data‐to‐data), one RD/WR (data‐to‐address), zero WR (data‐to‐ data), and one WR cycle hold. An optimum bus access will not create a significant increase in performance in the EV‐OXU200‐PCI system. For better performance evaluation, the OXU200 should be embedded directly on the system bus using the EV‐OXU200 board.
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PCI104 Bridge Board EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide This page is intentionally blank 3—4 External—Free Release UG-0038 Mar 07...
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Chapter 4 Schematics Overview This chapter provides the EV‐OXU200 and PCI104 schematics. The EV‐OXU200 uses a dual footprint so either the LQFP100 (U4) or the BGA64 (U3) package can be installed, but not both. UG-0038 Mar 07 External—Free Release 4—1...
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Schematics EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Figure 4-1 EV-OXU200 Top-Level Schematic 4—2 External—Free Release UG-0038 Mar 07...
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EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Schematics Figure 4-2 EV-OXU200 Test Headers UG-0038 Mar 07 External—Free Release 4—3...
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Schematics EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Figure 4-3 EV-OXU200 PC104 Connectors 4—4 External—Free Release UG-0038 Mar 07...
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EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Schematics Figure 4-4 OXU200 Schematic UG-0038 Mar 07 External—Free Release 4—5...
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Schematics EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Figure 4-5 EV-OXU200 Clocks 4—6 External—Free Release UG-0038 Mar 07...
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EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Schematics Figure 4-6 EV-OXU200 Power Distribution UG-0038 Mar 07 External—Free Release 4—7...
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Schematics EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Figure 4-7 PCI104 Top-Level Schematic 4—8 External—Free Release UG-0038 Mar 07...
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EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Schematics Figure 4-8 PCI104 PCI Connector UG-0038 Mar 07 External—Free Release 4—9...
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Schematics EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Figure 4-9 PCI9030 Bridge Chip 4—10 External—Free Release UG-0038 Mar 07...
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EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Schematics Figure 4-10 PC104 Connectors UG-0038 Mar 07 External—Free Release 4—11...
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Schematics EV-OXU200-PCI and EV-OXU200 Evaluation Board User Guide Figure 4-11 PC104 Expansion ROM 4—12 External—Free Release UG-0038 Mar 07...
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