Denon DN-D4500 Service Manual page 12

Pin No. Pin Name
34 PC5,NMI_
35 RST_
36 PC0
37 P76,TM13IOA
38 P60,IRQ0
39 P61,IRQ1
40 P62,IRQ2,TM10IOA FSYNC2
41 P63,IRQ3,TM10IOB DQSY1
42 P64,IRQ4
43 P65,IRQ5,TM12IOA
44 P66,IRQ6
45 P67,IRQ7
46 P70,TM13IOB
47 P71
48 PD2,DMAACK0_
49 PD3,TM3IO
50 VDD
51 P77,TM14IOA
52 P72,TM14IOB
53 P73
54 P74
55 P75,TM12IOB
56 PA0,SBI0
57 PA1,SBO0
58 PA2,SBT0
59 PA3,SBI1
60 PA4,SBO1
61 PA5,SBT1
62 PB0,SBI2
63 PB1,SBO2
64 PB2,SBT2
65 PB3,SBI3
66 PB4,SBO3
67 PB5,SBT3
68 VDD
69 VSS
70 AVSS
71 Vref-
72 P80
73 P81
74 P82
75 P83
76 P84
77 P85
78 P86,AD06
79 P87,AD07
80 PD4
81 PD5
82 P90
83 P91
84 P92
85 P93
86 Vref+
87 AVDD
88 P94
89 P95
90 P96,DAC2
91 P97,DAC3
92 PC6,BREQ_
93 PC7,BRACK_
94 WEL_
95 P51
96 RE_
97 CS2_
98 VDD
99 VSS
Simbol I/O DET
NMI I -
RST_ I -
_MUTE O
LOAD2 O
FSYNC1 I
BLKCK1 I
I
I
O
O
BLKCK2 I
DQSY2 I
EJECTSW2 I
LED2 O
CHGOFT1 O
DAC1MLD O
VDD - -
LOAD1 O
MON2_M1 I
_LSI_RESET1 O
MLD1 O
_LSI_RESET2 O
STAT1 I
MDATA1 O
MCLK1 O
STAT2 I
MDATA2 O
MCLK2 O
DSPTXD(RXD) I
DSPRXD(TXD) O
O
RXDRC I
TXDRC O
O
VDD - -
VSS - -
AVSS - -
Vref- - -
OPENSW1 I
CLOSESW1 I
INSW1 I
FPLAY1 I
FCUE1 I
FPLAY2 I
FCUE2 I
MON2_M2 I
MLD2 O
CHGOFT2 O
DAC2MLD O
O
DEBUG1 I
DEBUG2 I
Vref+ - -
AVDD - -
LDEND1 I
DSPIF1 O
DSPIF0 O
_DSPRES O
_BREQ I
_BRACK O
WE_ O -
_BOOT O
RE_ O -
CS2_ O -
VDD - -
VSS - -
Ext Ini Res
- - - Connect to Power
- - - ucom reset
Pd L Mute signal (L: Mute)
- Tray Loading / Eject signal (PWM output) (Driver2)
iPu X2: Clock for playback interrupt input / X1: LRCK (MP3)
iPu Sub cord clock interrupt (Servo DSP1)
iPu X2: Clock for playback interrupt input / X1: LRCK (MP3)
iPu CD-TEXT DQSY interrupt (Servo DSP1)
iPu
iPu
iPu Sub cord clock interrupt (Servo DSP2)
iPu CD-TEXT DQSY interrupt (Servo DSP2)
iPu CD2 Eject SW
Pu L Tray LED (CD2)
Pu L H Off-track signal (CD1)
iPu H Hiz PCM1748_1 Control Latch output signal
- - - Power (+3.3V)
- Hiz Tray Loading / Eject signal (PWM output) (Driver1)
iPu Servo DSP1 monitor signal 2
Pd L L Servo DSP1 / 2 reset signal
iPu H Hiz Servo DSP1 latch output signal
Pd L L Not used
iPu Servo DSP1 interface receive (clock sync)
Servo DSP1 interface send (clock sync)
Servo DSP1 interface clock (clock sync)
iPu Servo DSP2 interface receive (clock sync)
Servo DSP2 interface send (clock sync)
Servo DSP2 interface clock (clock sync)
Pu H DSP interface receive (UART)
Pu H DSP interface send (UART)
iPu L
Pu RCD45 interface receive (UART)
Pu RCD45 interface send (UART)
iPu L
- - - Power (+3.3V)
- - - GND
- - - Analog ref. GND for A/D conversion, GND
- - - Analog ref. V for A/D conversion, GND
Pu CD1 Tray open SW
Pu CD1 Tray close SW
Pu CD1 Inner SW
Pu Fader PLAY1 input
Pu Fader CUE1 input
Pu Fader PLAY2 input
Pu Fader CUE2 input
iPu Servo DSP2 monitor signal 2
iPu Servo DSP2 latch output signal
Pu Off track signal (CD2)
iPu PCM1748_2 Control Latch output signal
iPu Reserved
iPu
DSP → SYSTEM Reserved (CD1)
iPu
DSP → SYSTEM Reserved (CD2)
- - - Analog ref. V for A/D conversion, +3.3V
- - - Power (+3.3V)
iPu Loading end (CD1)
iPu Flag1 for DSP
iPu Flag0 for DSP
Pd DSP reset signal L: RESET
Pu Bus request signal
Pu Bus request accept signal
Pu - H Ext. memory write enable (Lower 8 bit)
Pu DSP boot start signal L: START
Pu - H Ext. memory read enable
- - - Ext. memory chip select 2 (Not used)
- - - Power (+3.3V)
- - - GND
12
DN-D4500 / BU4500
Function
L:ON
L:ON
L:ON