4
Internal block diagram
DATA
CLR
A2
A1
A0
WR
RD
CS
ODEN
5
I/O: CXD1095Q (IC8) pin signal
Signal
Pin No.
Port
1
NC
2
NC
3
PB1
4
PB2
SRES
5
PB3
6
PB4
7
PB5
8
PB6
9
PB7
DVBIAS
10
VSS
11
PC0
THV/MHV
8
8
8
8
8
4
CONTROL
IN/OUT
H/L
name
DTR
OUT
L
OUT
H
TC
OUT
H
TRC
OUT
H
RRC
OUT
H
PR
OUT
H
OUT
H
VSS
OUT
H
8
LATCH
8
LATCH
8
LATCH
8
LATCH
4
LATCH
DATA
SELECT
OR
Option receive allow signal
Option reset signal
Total counter control signal
Transport clutch control signal
Resist roller clutch control signal
Power relay control signal
Developing bias control signal
Power (GND)
Transfer/main charger control signal
12 – 9
8
PA
8
PB
8
PC
8
PD
4
PE
Specifications