Denon DRA-697CI Service Manual page 14

AK4385 (IC 207) XM-READY P.W.B.
Pin function
No. Pin Name
1 MCLK
2 BICK
3 SDTI
4 LRCK
5 PDN
6 CSN
7 CCLK
8 CDTI
9 AOUTR-
10 AOUTR+
11 AOUTL-
12 AOUTL+
13 VSS
14 VDD
15 DZFR
16 DZFL
Note: All input pins should not be left floating.
SN74LV08A (IC 204) XM-READY P.W.B.
SN74HCT08 (IC 205, 206, 211) XM-READY P.W.B.
1A V
1
14
CC
1B 4B
2
13
1Y 4A
3
12
2A 4Y
4
11
2B 5 3B
10
6
2Y 3A
9
7
GND 8 3Y
MCLK
1
BICK
2
SDTI
3
LRCK 4
PDN 5
CSN
6
CCLK
7
CDTI
8
I/O Function
I Master Clock Input Pin
An external TTL clock should be input on this pin.
I Audio Serial Data Clock Pin
I Audio Serial Data Input Pin
I L/R Clock Pin
I Power-Down Mode Pin
When at "L", the AK4385 is in the power-down mode and is held in reset.
The AK4385 should always be reset upon power-up.
I Chip Select Pin
I Control Data Input Pin
I Control Data Input Pin
O Rch Negative Analog Output Pin
O Rch Positive Analog Output Pin
O Lch Negative Analog Output Pin
O Lch Positive Analog Output Pin
- Ground Pin
- Power Supply Pin
O Rch Data Zero Input Detect Pin
O Lch Data Zero Input Detect Pin
16
15
14
13
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View
12
11
10
9
14
DRA-697CI
DZFL
DZFR
VDD
VSS
AOUTL+
AOUTL-
AOUTR+
AOUTR-