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Block Diagram (SODC : MN103SC7G)
FEP
DRC
LDD
ANALOG
FEP
SERVO
debugger
Watchdog
Formatter
CIRC
DMA bus
ODC
CD
(ECC command)
Write
Internal
data memory
On-Chip
Debugger
Resistor bus
Interrupt
Timer
Timer
ion
DVD/CD
DVD
error
correction
eDRAM
I/F
System
I/F
32 bit
Bus
control
CPU
General-
Purpose
PWM
Ports
5-38
HOST
ATAPI
I/F
eDRAM
16 Mbit
16.9 MHz
Clock
Generator
Flash
ROM
2 Mbytes
Serial
I/F