Memory Interface - Panasonic EB-GD90 Technical Manual

GEMINI

7.2.3 Memory Interface

The memory interface allows the 32 bit CPU to access 16 and 8 bit devices, and allows the addition of wait states to memory
access. The memory interface allows between 0 and 7 wait states to be added. The ROM area is hardware write protected, a
FLASH write enable bit in the ROM wait state configuration register can be used to enable write access the ROM area.
7.2.4 Interrupt Handler
The ARM CPU has two interrupts, FIQ is a Fast non-maskable interrupt and IRQ is a standard maskable interrupt.
Gemini has 11 interrupt sources. The Interrupt handler assigns priorities to these interrupts and routes them to either the FIQ
or IRQ inputs of the ARM CPU. Additionally, the interrupt handler controls waking up of the CPU on receiving an unmasked
interrupt, if the CPU is in sleep mode.
For GD90 the FIQ interrupt is reserved for the power supply fail priority interrupt.
Issue A
Revision 0
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Device Name Start address
ROM 0000:0000
RAM 0020:0000
BUS CNTRL 0040:0000
API RAM 0050:0000
APIC 0050:4000
TPU RAM 0050:4400
SIM 0050:4800
TSP 0050:4C00
INTH 0050:5000
TPU REG 0050:5400
CLKM 0050:5800
TIMER 0050:5C00
APIF 0050:6000
UWIRE 0050:6400
ARMIO 0050:6800
8251 0050:6C00
CS2 0060:0000
nCS0 0080:0000
nCS1 00A0:0000
Interrupt Level Assignments
Interrupt source Description
IRQ_TIM1 Buzzer timer
IRQ_TIM2 operating system timer
IRQ_API DSP Interface interrupt
IRQ_EXT Power supply fail interrupt
IRQ_USART UART Interrupt
IRQ_ARMIO Keypad Interrupt
IRQ_FRAME Frame Interrupt
IRQ_PAGE Page Interrupt
IRQ_TIM_GSM
IRQ_TSP Timed serial port Interrupt
IRQ_SIM SIM Interrupt
IRQ_F_USART Fast interrupt from USART
IRQ_RSS Radio subsystem interrupt
CPU Memory MAP
Size Use
2M FLASH 2 Mbytes
2M RAM 256 kbytes
1M wait state registers
8k CPU/DSP shared ram
1k CPU/DSP interface controller
1k GSM timer Microcode RAM
1k SIM interface
1k Timed Serial port
1k Interrupt controller
1k GSM timer registers
1k Clock control module
1k software timers
1k ARM peripheral interface
1k Synchronous Serial port
1k Keypad, buzzer, LCD & I/O
1k UART
2M LCD driver
2M Extended I/O
2M not used
Interrupt detection
Edge sensitive
Edge sensitive
Rising Edge sensitive
Low Level sensitive
Level sensitive
Low for 1 clock period
Edge sensitive
Edge sensitive
Edge sensitive
Edge sensitive
Level sensitive
Level sensitive
Edge sensitive
Section 7
– 32 –
Bus width
16 bits
8 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
16 bits
8 bits
8 bits
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MCUK981201G8
Technical Guide