System Control/Signal Processor Block Diagram - Sony DVP-NS50P Service Manual

Q Q
3 7 6 3 1 5 1 5 0

3-3. SYSTEM CONTROL/SIGNAL PROCESSOR BLOCK DIAGRAM

MV-045 BOARD
(SEE PAGE 4-7 to 4-8)
T E
L 1 3 9 4 2 2 9 6 5 1 3
IC103
EEPROM
w w w
.
IC104
64M SDRAM
146,147,149~151,158~160 115,117,118,120,121,123~126,128~133,135
SCL 6 102 SCL
SDA 5 103 SDA
228 229
9 IC101 228
X102
3.3Vp-p
27MHz
8 IC101 7 IC101
203 202
x a o 0.7Vp-p
y
H
H
i
3-5
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8
IC102
16M ROM
138 139 140 142 156 157 143 145 113 137 53~61,67~72,74~76,78,89,92,93 81~84,86~88,91
IC101 Q Q
3 7 6 3
CXD9849R
MICROPROCESSOR
AVDECODER
SERVO DSP
209 203 202 200 198 194 196
6 IC101 C/BAR PB IC101 C/BAR PB IC101 C/BAR PB
200 5 198 4 199
u 1 6 3 0.7Vp-p
1Vp-p
1Vp-p
1Vp-p
H H H
.
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2 4
9 9 8
IOOE 79
IOWR 66
IOCS 77
10 IC101
156
3.3Vp-p
110MHz
RESET IC
IC 108
1
1 5 1 5 0 8 9 2 4
CN 106
IFBSY 105
IFSCK 99
IFSDO 98
XIFCS 100
IFSDI 101
PRST 110
A_MUTE
TO MV-045
AUDIO
ABCK
ABCK 214 (SEE PAGE 3-10)
ALRCK
ALRCK 213
ACLK 215 ACLK
SPDIF 225 SPDIF
TO MV-045
AUDIO
XRST 220 XRST
(SEE PAGE 3-9)
MAMUTE 176 MAMUTE
ASDATA4 222 ASDATA4
11 IC101 215
3.3Vp-p
24MHz
V MUTE
C
Y
TO MV-045
V
VIDEO
Y/G
(SEE PAGE 3-11)
CB/B
CR/R
WIDE
IC101 C/BAR PB
3 196
m
286 mVp-p (NTSC)
300 mVp-p (PAL)
c o
H
3-6
DVP-NS50P/NS41P/NS52P
2
9 9
9 8 2 9 9
5 IFBSY
9 IFSCK
7 IFSDO
TO IF 124
4 XIFCS
INTERFACE
6 IFSDI
(SEE PAGE 3-14)
2 XSYSRST
10 V MUTE
14 A MUTE