Pioneer PDP-R03U Service Manual page 128

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• Pin Function
3 7 63 1515 0
Pin No. Pin Name
A 1, 40, 55, 80 DGND
45, 64, 100 DVDD
98 MRAS
99 MA8
2-9 MA7-MA0
10 MCAS
11 MWE
12 MOE
13-28 MIO15-MIO0
29 DGND
30 XI
31 XO
32 DVDD
B 33-36 HO3-HO0
37 HWCK
38 HRCK
39 HRST
41-44 HI3-HI0
46 AVDD
47 FSCO
48 AGND
49 AGND
50 FSCI
51 CPLL
52 RPLL
53 AVDD
54 CKMD
C
56 CLK8
57 RSTB
58 SLA0
59 SCL
TE
L 13942296513
60 SDA
61 ST0
62 ST1
63 NSTD
65-74 DYCO0-DYCO9
D
75 ALTF
76 CSI
77 TEST
78 LINE
79 KIL
81 AVDD
82 CBPC
83 ACO
84 AYO
85 CBPY
86 AGND
E
87 AGND
88 AYI
89 VCLY
90 VRBY
91 VRTY
92 AVDD
93 AVDD
94 VRTC
www
95 VRBC
96 ACI
97 AGND
F
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I/O
— Digital section grounding.
— Digital section power.
O External EDO memory RAS output.
O External EDO memory address output.
O External EDO memory address output.
O External EDO memory CAS output.
O External EDO memory WE output.
O External EDO memory OE output.
I/O External EDO memory data input/output.
— fsc generator digital section grounding.
I fsc generator reference clock input.
O fsc generator reference clock reverse output.
— fsc generator digital section power.
O External field memory data output.
O External field memory write clock output.
O External field memory read clock output.
O External field memory reset signal output.
I External field memory input.
— fsc generator DAC power.
— fsc generator fsc output.
— fsc generator DAC grounding.
— 8fsc-PLL grounding.
— 8fsc-PLL fsc input.
— 8fsc-PLL filter output.
I Test input.
— 8fsc-PLL power.
I CLK8 test mode select (L: Usual, H: Test mode).
O/I 8fsc clock output (8fsc clock input at CLK8 test mode).
I System reset input (Active Low).
(Active-Low reset pulse input from outside)
I PC bus slave address select input (L: B8/B9h, H: BA/BBh).
I PC bus clock input (To be connected to system's SCL line).
I/O PC bus clock input/output (To be connected to system's SDA line).
O nternal signal monitor output.
O Internal signal monitor output.
O Non-standard detection monitor output.
(L: Judged standard, H: Judged non-standard)
I/O EXADINS=0: Digital Y/C signal alternate output.
EXADINS=1: External Y-ADC data input.
(Non-used lower bits to be connected to GND with resistor in between)
O EXADINS=0: Digital Y/C signal alternate flag output (L: Y, H: C).
EXADINS=1: External Y-ADC 4fsc clock output.
I Composite sync input (Active Low).
I IC select test terminal (L: Usual operation, H: Test mode). (Connected to GND)
I Forced line-to-line process select input (L: Usual operation, H: Forced line-to-line
processing).
I External killer input (L: Usual operation, H: Forced Y/C separation stop).
— Y-DAC, C-DAC power.
O C-DAC phase compensation output.
O C-DAC analog C signal output.
O Y-DAC analog Y signal output.
O Y-DAC phase compensation output.
— Y-DAC, C-DAC grounding.
— Y-ADC grounding.
I Y-ADC analog composite signal/Y signal input.
O Y-ADC clamp potential output.
O Y-ADC bottom reference voltage output.
O Y-ADC top reference voltage output.
— Y-ADC power.
— C-ADC power.
O C-ADC top reference voltage output.
O C-ADC bottom reference voltage output.
x ao
I C-ADC analog C signal input.
y
— C-ADC grounding.
. i
PDP-R03U
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8
Pin Function
Q Q
3 6 7 1 3
u163
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3
4
2 9 9 4 2 8
1 5 0 5 8 2 9 9 4
m
co
4
9 9
2 8 9 9