Yamaha RX-V1700 Service Manual page 116

A B C
RX-V1700/DSP-AX1700
D-VIDEO 2/2
1
D-VIDEO
-4.9 -4.9
1.5 0.7
5.1
1.2
0.7
0 0
0.1 5.1
5.1 0.5
2
-4.9
-4.9
1.0 0.5
5.1
0.7
0 0
1.0 0
5.1
0.5
3
0
0.2
A-4
0
4
0 A/D
0 VIDEO DETECTOR
0
0
0
3.3
1.6
0
0
0
0
0
0
1.3
0
0
0
5
IC148: M30845MW-001-GP IC149: W9816G6CH -7
Single chip 16/32-bit microprocessor 512k x 2 banks x 16 bits SDRAM
6
8 8 8 8 8 8 8
CLK 35
Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6
CKE 34
< > < >
V CC2 V CC1
Peripheral Functions
A/D Converter: Clock Generation Circuit
1 circuit X IN - X OUT
Timer (16 bits) Standard: 10 inputs X CIN - X COUT RAS
(2)
Timer A: 5 channels Maximum: 34 inputs On-chip Oscillator
Timer B: 6 channels
PLL Frequency Synthesizer CAS
UART/Clock Synchronous Serial I/O:
Three-Phase Motor Control Circuit 5 channels DMAC WE
Watchdog Timer (15 bits) X/Y Converter: DMACII
16 bits x 16 bits
A10 20
D/A Converter: CRC Calculation Circuit (CCITT):
8 bits x 2 channels CAN Module: 1 channel X 16 +X 12 +X 5 +1
M32C/80 series CPU Core
Memory
Intelligent I/O
R0H R0L FLG
ROM
R1H R1L INTB
Time Measurement: 8 channels
7
Waveform Generating: 8 channels R2 ISP
Communication Functions:
R3 USP
Clock Synchronous Serial I/O, UART, RAM
HDLC Data Processing A0 PC
A1 SVF
FB SVP
Multiplier
SB VCT
< V > < V >
CC1 CC2
Port P14 Port P15 Port P11 Port P12 Port P13
7 8 5 8 8
(Note 1)
NOTES:
1. Ports P11 to P15 are provided in the 144-pin package only.
2. Included in the 144-pin package only.
8
IC146: MS2-N
Video Processor
Video Input
Interface
Test
Gen
BT.656 Test
Output
Gen
Path
4:4:4,
NRF
4:2:2 or
BT.656
ACE
Video
Measuremant
DI ACE IEF STE TCC Output
Auxiliary Sync
Input Separator
&
Auxiliary Coast Gen
PMR
Output
9
Clock
2 I C / 4-wire SDRAM Control
Generator MS2 Controller
CPU Interface Controller Output
CPU Control
1M x 16-bit SDRAM
10
# All voltages are measured with a 10MΩ/V DC electronic voltmeter.
# Components having special characteristics are marked s and must be replaced
with parts having specifications equal to those originally installed.
# Schematic diagram is subject to change without notice.
116
D E F
1.6 0
3.1 0.1
3.3 0.4
3.3 0.4
2.6 0.4
0 0.5
0 0.6
0 0.2
4.9 0.3
3.3
3.3 0
0 0
1.3 0
0 0.3
1.3
0 0 0.2
1.6 0
0 0.2
0.7
2.4 0 0.4
0.7 0
3.3 0.4
2.5 2.5
3.3 0.4
0 0
0 0.5
2.5 0.9
4.9 0.6
0.5 0
3.3 0
0.7 0.1
0.5 2.4
1.6 0.1
0.2 0
1.2 0
2.4 0.2
1.2 0
0 0.2
3.3
3.3
0.9 0.3
0 0.3
2.4 0.4
0 0.5
0 0.4
4.9 0.6
3.3 0
VIDEO ENCODER
D/A
0.1 0
0 0.1
0
0
0
0
3.3 0.4
1.7 0.4
3.3 0.4
3.3 0
0 0
0 0.2
0 0.3
0 0.3
0 0.2
0 0.2
0 0.4
0 0.4
3.3 0.4
0 3.3 0
0
0
0
0.1 0
0 1.2 0.3
0 0.3
0
3.3 0 0.3
0.3
3.3 0.4
0 0.1 0.4
0.5
3.3 1.2
3.1 1.6 0.4
0 0.6
3.3
0 3.3 0
0
0.1
0.5
0
0
3.3
0
3.3
3.2
0
0
CLOCK
BUFFER
COLUMN DECODER
CS 18 CONTROL
SIGNAL
R
17
GENERATOR O
COMMAND W
16 DECODER
D CELL ARRAY
2 DQ0
E
15 BANK #0
C
3 DQ1
O
D
E 5 DQ2
R
6 DQ3
SENSE AMPLIFIER
8 DQ4
9 DQ5
MODE 11 DQ6
A0 21
REGISTER
12 DQ7
A3 24 ADDRESS
REFRESH DQ
BUFFER
A4 27 COUNTER BUFFER 39 DQ8
40 DQ9
A9 32
42 DQ10
BA 19
43 DQ11
45 DQ12
46 DQ13
REFRESH COLUMN
COLUMN DECODER 48 DQ14
COUNTER COUNTER
R
49 DQ15
O
W
D CELL ARRAY
E BANK #1
C
O
D
E
14 LDQM
R
36 UDQM
SENSE AMPLIFIER
IC138: ADV7322KSTZ
Multiformat 11-bit HDTV video encoder
STAN DARD DEFINITION ADV7322
CONTROL BLOCK
COLOR CONTROL
BRIGHTNESS
DNR 11-BIT
GAMMA DAC
PROGRAMMABLE
FILTERS
O 11-BIT
SD TEST PA TTERN
V DAC
E
R
D 11-BIT
Y7–Y0 S
E PROGRAMMABLE DAC
C7–C0 A
M RGB MATRIX
S7–S0 M
U
P 11-BIT
X
L DAC
I
HIGH DEFINITION N
11-BIT
CONTROL BLOCK G
DAC
HD TEST PA TTERN
11-BIT
DAC
COLOR CONTROL
HSYNC
TIMING ADAP TIVE FILTER CTRL
VSYNC
GENERATOR SHARPNESS FILTER
BL ANK
I 2 C
INTERFA CE
CLKIN_A PLL
CLKIN_B
IC156, 157: NJM2885DL1-33
Low dropout voltage regulator
VIN 1
Bandgap
Reference
GND 2
G H
SDRAM
0
3.3 0
3.1 0
0
3.3
0 1.6
3.1
3.3
2.6
0
De-INTERLACER 1.8
0
0
1.6 1.8
1.8 0
0.3 3.3
0.2 0
0.2 0
0 0
0.1 3.3
0.1 0.4
0.1 3.3
0.1 0
0
0.1
0.1 2.4
0
0.1
0 0.4
0
0
0 0.9
0.4 0.9
1.2 2.4
1.6 0
3.3
0
3.0
0.4 3.3
0.4 3.3
0.4 3.3
0.4 0
0.4 0
0
3.3
0
3.3
3.3 3.3
0 3.3
3.3 1.4
MICROPROCESSOR
0.4
0.4 3.1
(VIDEO)
3.1
0.4
0.4 3.3
3.3
0
4.9
0
0
3.3
0.1
4.9 3.3
0 3.3
0 0
4.9 3.1
3.3
4.9
0 4.9
4.9
4.9 0.1
4.9
0.1
0
5.0
0.1
0 0
4.9
4.9 B-1 4.9
4.9 4.9
5.1 4.9
4.9
3.3
4.9
3.3
3.3
3.2 3.3 4.9
3.3
5.2
3.3
0
2.3
0
0
IC158: NJM2391DL1-33 IC160: NJM2885DL1-25
Low dropout voltage regulator Low dropout voltage regulator
3 VOUT VIN 1
Thermal
Protection
Bandgap
Reference
GND 2
I J K
POINT A-4 Pin 38 of IC137
POINT B-1 Pin 20 of IC148
0
0.7
0
0.7
0
0
0.7
0
0
0
4.9
0
0
0
0
4.9
0
0.1
5.0
5.0
4.9
0.1 5.0
5.0
0.1
0.6
5.0
0.1
5.0 5.0
5.0
5.0
No replacement part available.
4.9
5.0
3.3
0
3.3 3.0
0
4.9
3.4 2.5
3.4 2.5
4.9 3.3
4.9 3.3 0
0
0
0
3.4
4.9 3.3 3.4 1.8
0
4.9 3.3
3.4
0
0
3.4 1.8
4.9 3.4
3.4 1.8
4.9 3.4
0
0
0
IC162: NJM2845DL1-18 IC172: SN74AHCT1G125DCKR
Low dropout voltage regulator Single bus buffer gate
3 VOUT
VIN 1 3 V OUT
Thermal Thermal
Protection
Protection OE 1 5 VCC
Bandgap
Reference
A 2
GND 3 4 Y
GND 2
L M N
IC137: ADV7401BSTZ-80
Multiformat SDTV/HDTV video decoder and RGB graphics digitizer
0.4 0
0.4 0.2
0.4 0.1
0.2 0.1
0.2 0.1
0.3 0.2
0.3
0.2
0.2 0.2
3.3
0.2
3.3 0
0.6 0
0.4 0
0.5 0.2
0.4 0 IC163: SN74AHCT08PWR
0.3 0
0.3 0 Quadruple 2-input positive-AND gates
0.3 0
0.3 0
3.3 0
1A 1 14 Vcc
3.3 0
1B 2 13 4B
0.2 0
0.2 0 1Y 3 12 4A
0.5 0
0.6 0 2A 4 11 4Y
0.5 0
0.4 0 2B 5 10 3B
0.4 0
0.4 0 2Y 6 9 3A
3.3 0
GND 7 8 3Y
3.3 0
IC140-145, 175-177: SN74LVC245APWR
Octal bus transceivers with 3-state outputs
1 20
DIR Vcc
A1 2 19 OE
3 18
A2 B1
A3 4 17 B2
5 16
A4 B3
A5 6 15 B4
7 14
A6 B5
A7 8 13 B6
9 12
A8 B7
GND 10 11 B8
IC133: LA73053-TLM-E
Analog dual operational amplifier
N.C. 1 36 N.C.
N.C. 2 35 N.C.
3
VIN1 34 +VCC1
+Vcc
DCCNT1 4 33 VOUT1
6dB DR
GND 5 32 GND
VIN2 6 31 VOUT2
6dB DR
MUTE1 7 30 N.C.
VIN3 8 29 VOUT3
6dB DR
N.C. 9 28 -VCC1
N.C. 10 27 -VCC2
11
N.C. 26 N.C.
VIN4 12 25 +VCC2
+Vcc
DCCNT2 13 6dB DR 24 VOUT4
14
GND 23 GND
VIN5 15 22 VOUT5
6dB DR
MUTE2 16 21 N.C.
VIN6 17 20 VOUT6
6dB DR
-VCC4 18 19 -VCC3
IC136: SN74LVC2G125DCUR
Dual bus buffer gate
1OE 1 8 VCC
1A 2 7 2OE
2Y 3 6 1Y
GND 4 5 2A
1
1OE
6 6
1A 1Y
7
2OE
3 3
2A 2Y
IC179: R3112N421A-TR-F IC180: R1131N181D
Low voltage detector with output delay Voltage regulator
V DD 2 1 OUT V DD 6 1 V OUT
R D
Vref
Vref
Current Limit
GND CE GND
3 3 2, 5
5
C D