Sony HCD-DZ230 Service Manual page 63

Pin No. Pin Name
48 RESERVED
49 USB_VDD3
50 SPFG
51 MSW
52 CKSW
53 OCSW
54 EEWP
55 DVDD18
56 to 64 HA2 to 8, 18, 19
65 DVDD3
66 XWR
67 to 75 HA16 to 9, 20
76 XROMCS
77 HA1
78 XRD
79, 80 HD0,1
81 DVSS
82 to 86 HD2 to 6
87 HA21
88 RESERVED
89 HD7
90 DVSS
91, 92 HA17, 0
93 DVDD18
94 RESERVED
95 RESERVED
96 DVDD3
97 IFSDO
98 IFCK
99 xIFCS
100 IFSDI
101 SCL
102 SDA
103 HDMI_SCL
104 HDMI_SDA
105 RXD
106 TXD
107 ICE
108 xSYSRST
109 RESERVED
110 xTXINT
111 DQM0
112 IFBSY
113 to 117 RD7 to 3
118 DVDD3
119 to 129 RD2 to 0, 15 to 8
130 LIMITSW
131 DVDD3
132 DQM1
I/O
— USB port DMINUS pin for HS DL (not used (Open))
— Power supply (SW+3.3V)
I Spindle FG input
O DVD/CD switch (H:DVD / L:CD)
I CKSW input
I OCSW input
O EEPROM Write Protect control (L:Write allowed)
— Power supply (+1.8V from IC1110)
O Host address bus 2 to 8, 18, 19 output to Flash ROM (IC1102)
— Power supply (SW+3.3V)
O Write enable output to Flash ROM (IC1102) (active Low)
O Host address bus 15 to 9, 20 output to Flash ROM (IC1102)
O Chip select output to Flash ROM (IC1102) (active Low)
O Host address bus 1 output to Flash ROM (IC1102)
O Read enable output to Flash ROM (IC1102) (active Low)
I/O Host data bus 0,1 input/output for Flash ROM (IC1102)
— Ground terminal
I/O Host data bus 2 to 6 input/output for Flash ROM (IC1102)
O Host address bus 21 output to Flash ROM (IC1102)
— Not used (Open)
I/O Host data bus 7 input/output for Flash ROM (IC1102)
— Ground terminal
O Host address bus 17, 0 output to Flash ROM (IC1102)
— Power supply (+1.8V from IC1110)
— Not used (Open)
— Not used (Open)
— Power supply (SW+3.3V)
O Ext. CPU Serial data output (H/W method)
O Ext. CPU Serial clock (H/W method)
O Chip select for Ext.CPU (Low Active, H/W method)
I Ext. CPU Serial data input (H/W method)
O IIC clock output to E2PROM and HDMI controller
I/O IIC data input/output for E2PROM and HDMI controller
O HDMI DDC line SCL
I/O HDMI DDC line SDA
I RS232C RXD signal input from Jig
O RS232C TXD signal output to Jig
O ICE mode enable (not used (Open))
I Reset input from system controller (IC501) (active Low)
I IR control signal input (not used (Open))
I Interrupt signal from HDMI controller (not used (Fixed "H" (SW+3.3V)))
O Lower byte mask output to SDRAM (IC1104) (H:Mask / L:Enable)
I Ready/Busy interrupt signal input from system controller (IC501) (H:Busy / L:Ready)
I/O Data bus 7 to 3 input/output for SDRAM (IC1104)
— Power supply (SW+3.3V)
I/O Data bus 2 to 0, 15 to 8 input/output for SDRAM (IC1104)
I LIMITSW signal input
— Power supply (SW+3.3V)
O Upper byte mask output to SDRAM (IC1104) (H:Mask / L:Enable)
HCD-DZ230/DZ231/HDZ235
Description
63