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9.16 Sil 9023 Dual Input RX
RX Config. I2C Addr. Select
State
Address
Low
0x60/0x68 (Default)
High
0x62/0x6A
V33
R45
4.7K_NC
RCLK48B
R46
Default
4.7K
V33
L12
PBY20-221C
C39
C40
C41
C42
22U
.1C
102
102
V33
L17
PBY20-221
L18
PBY20-221
LAYOUT: Place xtal
close as possible to chip
V18RX
V33
U13
AIC1117-1.8-SOT223
L19
PBY20-221
I
O
VI
VO
O1
TAB
C96
C97
100U
.1
ViewSonic Corporation
RESETn
R38
P{9}
RESETn
DSDA1
{3}
DSDA1
DSCL1
DSCL1
{3}
DSDA0
{3}
DSDA0
DSCL0
{3}
DSCL0
U12
1
56
Small
TP1
RSVD_A
RR0XC-
39
{3}
RR0XC-
R0XC-
RR0XC+
40
{3}
RR0XC+
R0XC+
RR0X0-
43
{3}
RR0X0-
R0X0-
RR0X0+
44
{3}
RR0X0+
R0X0+
RR0X1-
47
{3}
RR0X1-
R0X1-
RR0X1+
48
{3}
RR0X1+
R0X1+
RR0X2-
51
{3}
RR0X2-
R0X2-
RR0X2+
52
{3}
RR0X2+
R0X2+
RR1XC-
58
{3}
RR1XC-
R1XC-
RR1XC+
59
{3}
RR1XC+
R1XC+
RR1X0-
62
{3}
RR1X0-
R1X0-
RR1X0+
63
{3}
RR1X0+
R1X0+
RR1X1-
66
{3}
RR1X1-
R1X1-
RR1X1+
67
{3}
RR1X1+
R1X1+
RR1X2-
70
{3}
RR1X2-
R1X2-
RR1X2+
71
{3}
RR1X2+
R1X2+
38
AVCC
42
AVCC
46
AVCC
LAYOUT: Place capacitors as
50
AVCC
close as possible to chip
57
AVCC
61
AVCC
65
AVCC
C43
C44
C45
C46
C47
C48
C49
69
AVCC
41
AGND
102
102
102
102
102
102
102
45
AGND
49
AGND
53
AGND
60
AGND
64
AGND
68
AGND
72
AGND
V33
L14
PBY20-221
37
PVCC0
55
C59
PVCC1
C60
C61
22U
102
102
54
PGND
V18RX
L15
PBY20-221
74
CVCC18
35
C65
CVCC18
C66
C67
22U
102
102
73
CGND
36
CGND
V18RX
98
XTALVCC
99
REGVCC
94
AUDPVCC18
C75
C78
C76
C77
C79
C80
C81
C82
95
AUDPGND
22U
.1
102
22U
.1
102
.1
102
C85
33P
RXO
R49
33
Y1
R50
28.322MHz
as
1M
3
XO
C86
33P
XI
R0PWR5V
{3}
R0PWR5V
R1PWR5V
{3}
R1PWR5V
V18RX
V18RX
PBY20-221
C98
C99
.1
100U
46
N4261w-1M
Confidential - Do Not Copy
OVCC
47
SiI 9023
144-Pin TQFP
MCLKOUT
MUTEOUT
EVENODD
R52
4.7K
V18RXVCC
V18RXVCC
L20
C88
C87
C89
C90
C91
C92
C93
C94
C95
.1
22U
.1
.1
.1
102
102
102
.1
RDE
R39
22
P0APEN
P0APEN
RVSYNC
R42
22
P0AVS
P0AVS
RHSY NC
R43
22
P0AHS
P0AHS
RODCK
R44
22
P0ACLK
P0ACLK
RX_D0
P0ABLU2
144
1
8
Q0
RX_D1
RP1
P0ABLU3
143
2
7
Q1
RX_D2
22
P0ABLU4
142
3
6
Q2
RX_D3
P0ABLU5
141
4
5
Q3
RX_D4
P0ABLU6
140
1
8
Q4
RX_D5
RP2
P0ABLU7
137
2
7
Q5
RX_D6
22
P0ABLU8
136
3
6
Q6
RX_D7
P0ABLU9
133
4
5
Q7
RX_D8
P0AGRN2
132
1
8
Q8
RX_D9
RP3
P0AGRN3
131
2
7
Q9
RX_D10
22
P0AGRN4
130
3
6
Q10
RX_D11
P0AGRN5
129
4
5
Q11
RX_D12
P0AGRN6
126
1
8
Q12
RX_D13
RP4
P0AGRN7
125
2
7
Q13
RX_D14
22
P0AGRN8
124
3
6
Q14
RX_D15
P0AGRN9
123
4
5
Q15
RX_D16
P0ARED2
119
1
8
Q16
118
RX_D17
RP5
2
7
P0ARED3
Q17
RX_D18
22
P0ARED4
117
3
6
Q18
RX_D19
P0ARED5
116
4
5
Q19
RX_D20
P0ARED6
113
1
8
Q20
RX_D21
RP6
P0ARED7
112
2
7
Q21
RX_D22
22
P0ARED8
111
3
6
Q22
RX_D23
P0ARED9
110
4
5
Q23
R47
33
RCLK48B
107
CLK48B
R48
47_NC
RP7
87
NC
HDMI_MCLK
88
1
8
HDMI_CL
2
7
HDMI_WS
86
3
6
SCK
I2S_DI2
85
4
5
WS
84
SD0
22
83
NC
82
NC
81
NC
78
SPDIF
C50
C51
C52
C53
C54
C55
77
102
102
102
102
102
102
17
NC
20
NC
14
NC
9
C62
C63
.1_NC
11
NC
C64
7
NC
102_NC
22U_NC
13
NC
PBY20-221
16
IOVCC
19
NC
C68
C69
C70
C71
C72
C73
8
NC
12
NC
102_NC
102_NC
102_NC
102_NC
102
.1
15
IOGND
18
NC
V33
6
NC
V18RX
22
VPP3318
21
CGND
C83
C84
.1_NC
.1
SiI 9021/9031
R51
180_NC
LAYOUT: Place resistor
close as possible to chip
SDA
SDA
P{9,12,14}
SCL
SCL
P{9,12,14}
P{8}
P{8}
P{8}
P{8}
P0ABLU[9:2]
P{8}
P0AGRN[9:2]
P{8}
P0ARED[9:2]
P{8}
HDMI_MCLK
P{12}
HDMI_CL
P{12}
HDMI_WS
P{12}
I2S_DI2
P{12}
OVCC
V33
OVCC
PBY20-221
L13
C58
C56
C57
102
.1
22U
V33
L16
C74
22U
as
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