Onkyo DV-SP300 Service Manual page 29

MICROPROCESSOR TERMINAL DESCRIPTION
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PIN NUMBER DESCRIPTION
112 JTAG
113 JTAG
114 TIMER
115 TIMER
116 TIMER
117 EMI Interface
118 EMI Interface
119 -
120 CLOCK & RESET
121 -
122 CLOCK & RESET
123 CLOCK & RESET
124 CLOCK & RESET
125 INTERRUPT
126 INTERRUPT
127 INTERRUPT
128 EMI Interface
129 EMI Interface
130 EMI Interface
131 EMI Interface
132 EMI Interface
133 EMI Interface
134 EMI Interface
135 EMI Interface
136 -
137 -
138 EMI Interface
139 EMI Interface
140 EMI Interface
141 EMI Interface
142 EMI Interface
143 EMI Interface
144 EMI Interface
145 EMI Interface
146 EMI Interface
147 EMI Interface
148 EMI Interface
149 -
PIN NAME MAIN FUNCTION
TDI TEST DATA IN
TCK TEST CLOCK
PWM2 PULSE WITDH MODULA2
PWM1 PULSE WITDH MODULA1
PWM0 PULSE WITDH MODULA0
CPU_OE OUTPUT_ENABLE
CPU_RAM_CLK SDRAM CLOCK
VDD2_5 2.5V POWER SUPPLY
PIX_CLK 27 MHz main clock
VSS GROUND
VDD_PLL VDD PLL=2.5V
VSS_PLL GND PLL=GND
RESET CHIP RESET
IRQ2[2] IRQ[2](MD_IRQ)
IRQ2[1] IRQ[1](ATAPI IRQ)
IRQ2[0] IRQ[0](SERVO_IRQ)
CPU_BE[0] BYTE0 ENABLE
CPU_BE[1] BYTE1 ENABLE
CPU_RW READ-NOT WRITE
CPU_WATE WATE STATE
CPU_CE[4] CHIP SEL.BANK3
CPU_CE[3] CHIP SEL.BANK2
CPU_CE[2] CHIP SEL.BANK1
CPU_CE[0] DARAM_RAS0
VDD3_3 3.3V POWER SUPPLY
VSS GROUND
CPU_RAS1 DARAM RAS
CPU_CAS[0] DARM CAS0
CPU_CAS[1] DRAM
CPU_DATA[0] DATA[0]
CPU_DATA[1] DATA[1]
CPU_DATA[2] DATA[2]
CPU_DATA[3] DATA[3]
CPU_DATA[4] DATA[4]
CPU_DATA[5] DATA[5]
CPU_DATA[6] DATA[6]
CPU_DATA[7] DATA[7]
VDD2_5 2.5V POWER SUPPLY
ALTERNATE FUNCTION
INPUT OUTPUT
-
-
VSYNC
BOOT FROM ROM3
HSYNC
-
-
-
-
-
-
-
-
-
-
-
- DQM[0]
- DQM[1]
- NOT_SDRAM_WE
-
- CS_SBU_BANK3
-
-
- SDRAM_RAS
-
-
- NOT_SDARAM_CS1
- SDARM CAS/CPU_ADR[22]
- NOT_SDARM_CS0
-
-
-
-
-
-
-
-
-
DV-SP300
TYPE REMARK
- I
- I
- I/O
- I/O
- I/O
- I/O
- O
- POWER
- I
- POWER
- POWER 2.5V
- POWER GND
- I
- I
- I
- I
O
O
O
- I
O
- O
- O
O
- POWER
- POWER
I/O
O
O
- I/O
- I/O
- I/O
- I/O
- I/O
- I/O
- I/O
- I/O
- POWER