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HEAD_INT
N3
KBR0, KBR1, KBR2
H2, H3, H1
( Keyboard )
KBC0, KBC1, KBC2, KBC3
K1, J4, J3, J2
BKLT_EN
K2
DP_EN
E10
KEYPAD
P4
HS_INT
DISPLAY
K4
VIB_EN
INTERFACE
LED_RED
M3
LED_GRN
M2
LS1_IN
E8
SIM
D6
LS2_IN
INTER
LS3_TX
E1
FACE
LS3_RX
E6
CLK_SELCT
C3
A1
TX_EN
D2
C1
DM_CS
F5
E2
CTM
TX_KEY
E4
E1
RX_EN
E2
MODULE
E3
E3
RX_ACQ
E4
M4
RESET
P2
( SDTX ) BDX
C6
( TX_CLK ) BCLKX
A2
SERIAL
( SCLK_OUT ) BCLKR
INTER
from / to MAGIC
A3
( SDFS ) BFSR
FACE
B4
( SDRX ) BDR
J 600
C4
DSC_EN_B+
13
J5
DSC
6
SCI_RX
D6
UART
( for RS232 )
7
INTERF.
A6
SCI_TX
4
BATT FDBK
14
EXT_B+
EXT_B+
2
SW_RF
8
BATT FDBK
9
On/Off
1
GND
3
GND
10
GND
G5
GND
15
( Ext Accessory Sense)
5
MAN_TEST_AD
A1
DSC_EN_AD
B2
A2
DOWNLINL_AD
B3
BATT_THERM
D9
ISENSE
C4
RESET
D2
11
UPLINK
C3
12
DOWNLINK
J2
MIC
H3
SPKR
ALRT
A4
C14, D4, E12, H4, J10, K6, N12
B5, B9, B10, G12, K14, L11, N8
( CE ) MQSPI_CS1
U700
L8
WHITE_CAP
( SPI_CLK ) MOSPI_CLK1
SPI
M8
( SPI_DATA ) DX1
INTERFACE
M7
M
E
M
O
R
Y
( Flip Con. )
R_W
I
CPU
N
T
C9
E
E9
R
D11
F
A
D9
C
Baseband
E
A9
to Digital
Speech
CTM
F3
DSP
-5V_EN
N6
A / D
CHARGE
SPI
TIMER
INTERFACE
D7
K5 G14
RTC_BATT
F5
A7 B7
D9
C7
D6
SELECT
E8
SPI
REAL TIME
INTERFACE
SENSE
F7
CLOCK
CNTL
D10
CLK
F6
U900
RST
LEVEL
J7
SENSE
SIM_I/O
SHIFT
J8
G_CAP2
CNTL.
K7
G6
K10
H8
C8
G4
Logic Control
G9
VREF
REG.
V3
B5
REG.
J5
V2
REG.
A6
V1
REG.
VSIM
C6
Interface
REG.
A10, C10
Audio
Codec
VBOOST1
REG.
H6 H7 K9
J9
H9
K5 E10
B10
LX
CR901
Q938
L901
ALRT_VCC
B+
V2
V3
PRESENCE DETECT
( MAGIC SPI )
DATA BUS
ADDRESS BUS
V2
D6, E1
V2
A4, A6, F6
CE2
B2
U702
RESET
CE3
A1
SRAM
R_W
G6
CE0
CE1
LS_V1
STDBY
2
LS_V1
1
5
U901
-5V
EXT B+
BATT +
B+
U970
Q970
Q942
CR940
Q932
CR932
R932
I SENSE
CHRGC
BATT+
EXT_B+
6
J900
SIM
4
Con.
5
1
2
VSIM1
LS1_IN
LS2_IN
LS3_TX
LS3_RX
PWR_SW
STDBY
VREF
2.775V,for MAGIC
V3
1,8V, for WhiteCap
V2
2.775V, for WhiteCap logic outputs, RAM, FLASH, EEPROM
LS_V1
5.0V, for DSC Bus, Negative Voltage Regulator
VSIM1
3.0 or 5.0V, for SIM Card Circuit
V_BOOST1
Internal GCap use only (VSIM1, LS_V1)
Q938
BATT THERM / THERM
( WhiteCap )
VIB_EN
1
U801
4
5
B+
BATT SER DATA
U701
B4
EPROM
EEPROM
D7
F8
DEEP SLEEP
V1
CIRCUIT
KBR0, KBR1, KBR2
KBC0, KBC1, KBC2, KBC3
CHRG_EN
BATT +
Q634
Q635
BATT FDBK
GSM SERVICE SUPPORT GROUP
LEVEL 3 AL Block Diagram
Dualband Krunch
Ralf Lorenzen, Michael Hansen, Ray Collins
BKLT+
( Flip Con. )
J601
FLIP CON.
BATT+
1, 2, 3, 4, 5
6
SPKR +
7
SPKR -
8
VIB DRV
9
RTC BATT
10
11
BATT GND
12, 13, 14, 15, 16
GND
17, 18
R_W
1
J101
GND
2, 30, 32
A0
3
NC
4, 13, 17
D0 - D7
5, 8, 9, 10, 11, 12, 14, 18
6
RESET
DP_EN
7
15
-5V DV
V2
16
19
BKLT_EN
PWR_SW
20
21, 22, 23
24, 25, 26, 27
HS_INT
28
29, 31
BKLT+
( GCAP2 )
V2
3
5
LED_RED
Q805
6
( WhiteCap )
2
4
LED_GRN
Q805
1
RX SIGNAL PATH
TX SIGNAL PATH
MAIN VCO SIGNAL PATH
TUNING VOLTAGES
REFERENCE CLOCK
Orderable Part
Non - Orderable Part
10.01.00
Rev. 1.2
Page1
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