Sony D-EJ855 Service Manual page 20

D-EJ855
•
C601 CXD3029R
(RF AMP, DIGITAL SIGNAL PROCESSOR, DIGITAL SERVO PROCESSOR, D-RAM CONTROLLER)
Pin No. Pin Name
1 XRAS
XWE
2
3 to 6 D1, D0, D3, D2
7, 8 TEST1, TEST2
9 XCAS
10
WFCK
11 to 13 A9 to A7
14 DVSS
15 to 17 A6 to A4
18 XRDE
19 VDD0
20 CLOK
21 SDTO
22 SENS
23 XLAT
24
XSOE
25 SYSM
26
WDCK
27
SCOR
28 XRST
29 PWMI
30 XQOK
31 XWRE
32 R4M
33 VSS0
34 SQCK
35 SCLK
36
SQSO
37
XEMP
38
XWIH
39
SBSO
40 EXCK
41 XSTL
42 HVSS
43 HPL
44 HPR
45
HVDD
46
XVDD
47 XTAI
48 XTAO
49 XVSS
50
AVDD1
51 AOUT1
52 VREFL
53, 54 AVSS1, AVSS2
20
I/O
O Row address strobe signal output to the D-RAM (IC602)
O Data input enable signal output to the D-RAM (IC602)
I/O Two-way data bus with the D-RAM (IC602)
O
Output terminal for the test Not used (open)
O
Column address strobe signal output to the D-RAM (IC602)
O WFCK signal output terminal Not used (open)
O Address signal output to the D-RAM (IC602)
—
Ground terminal (for D-RAM interface)
O
Address signal output to the D-RAM (IC602)
I
D-RAM read enable signal input terminal Not used (open)
— Power supply terminal (digital system)
I Serial data transfer clock signal input from the system controller (IC801)
I Serial data input from the system controller (IC801)
O Serial data output to the system controller (IC801)
I Serial data latch pulse signal input from the system controller (IC801)
I Serial data output enable signal input from the system controller (IC801)
Analog muting on/off control signal input from the system controller (IC801)
I
"H": muting on
O GRSCOR signal output to the system controller (IC801)
O Subcode sync (S0+S1) detection signal output to the system controller (IC801)
I
Reset signal input from the system controller (IC801) "L": reset
I Spindle motor external control signal input terminal Not used (open)
I Subcode Q OK signal input terminal Not used (open)
I
D-RAM write enable signal input terminal Not used (open)
O System clock output to the system controller (IC801)
—
Ground terminal (digital system)
I SQSO readout clock signal input terminal Not used (fixed at "H")
I SENS serial data read clock signal input terminal Not used (fixed at "H")
O CD text data output terminal Not used (open)
O D-RAM read prohibition signal output terminal Not used (open)
O D-RAM write prohibition signal output terminal Not used (open)
O Subcode P to W serial data output terminal Not used (open)
O SQSO readout clock signal output terminal Not used (pull down)
Input terminal for the system clock frequency setting
I
"L": 16.9344 MHz, "H": 33.8688MHz (fixed at "L" in this set)
—
Ground terminal (for headphone)
O PDM signal output for L-ch headphone to the headphone amplifier (IC301)
O PDM signal output for R-ch headphone to the headphone amplifier (IC301)
— Power supply terminal (for headphone)
— Power supply terminal (for master clock)
I
System clock input terminal (16.9344 MHz)
O System clock output terminal (16.9344 MHz)
—
Ground terminal (for master clock)
— Power supply terminal (analog system)
O L-ch analog audio signal output
O L-ch reference voltage output terminal
—
Ground terminal (analog system)
Description