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6. Burst Definition
Notes:
1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the
first access within the block.
2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects
the first access within the block.
3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2
selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
Burst Type
Accesses within a given burst may be programmed to be either sequential or
interleaved; this is referred to as the burst type and is selected via bit A3. The ordering
of accesses within a burst is determined by the burst length, the burst type and the
starting column address, as shown in Burst Definition on page 11.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the
registration of a Read command and the availability of the first burst of output data. The
latency can be programmed 2 or 2.5 clocks.
If a Read command is registered at clock edge n, and the latency is m clocks, the data
is available nominally coincident with clock edge n + m. Reserved states should not be
used as unknown operation or incompatibility with future versions may result.
CONFIDENTIAL – DO NOT COPY
Page 7-36
File No. SG-0211
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