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3. Part of IC906 (H Driver) and IC901 (V Driver)
An H driver (part of IC906) and V driver (IC901) are neces-
sary in order to generate the clocks (vertical transfer clock,
horizontal transfer clock and electronic shutter clock) which
driver the CCD.
IC906 has the generation of horizontal transfer clock and the
function of H driver, and is an inverter IC which drives the
horizontal CCDs (H1 and H2). In addition the XV1-XV4 sig-
nals which are output from IC101 are the vertical transfer
clocks, and the XSG signal which is output from IC101 is su-
perimposed onto XV1 and XV3 at IC901 in order to generate
a ternary pulse. In addition, the XSUB signal which is output
from IC101 is used as the sweep pulse for the electronic shut-
ter, and the RG signal which is output from IC906 is the reset
gate clock.
VDC
VHH
5
19
VDC
VH
Level
IV1
20
conversion
VL
VDC
VH
Level
21
CH1
conversion
VL
VDC
VH
Level
IV3
22
conversion
VL
VDC
VH
Level
CH2
23
conversion
VL
VDC
VH
Level
CH3
24
conversion
VL
VDC
VH
Level
IV2
25
conversion
VL
VDC
VH
Level
IV4
26
conversion
VL
VDC
VH
Level
IV6
27
conversion
VL
VDC
VH
Level
IV5
28
conversion
VL
VDC
VH
Level
CH4
1
conversion
VL
VDC
VH
Level
2
CH5
conversion
VL
VDC
VHH
Level
3
ISUB
conversion
VL
Fig. 1-3. IC901 Block Diagram
VH
4
17
VM
VL
7
VM
18
VL
6
VL
3-level
VH
16
OV1
VM
VL
2-level
VM
15
OV2
VL
3-level
VH
14
OV3
VM
VL
3-level
VH
13
OV5
VM
VL
2-level
VM
12
OV4
VL
3-level
VH
11
OV7
VM
VL
3-level
VH
10
OV8
VM
VL
2-level
VM
9
OV6
VL
2-level
VHH
8 OSUB
VL
– 3 –
4. IC906 (H Driver, CDS, AGC and A/D converter)
IC906 contains the functions of H driver, CDS, AGC and A/D
converter. As horizontal clock driver for CCD image sensor,
HØ1 (A and B) and HØ2 (A and B) are generated inside, and
output to CCD.
The video signal which is output from the CCD is input to pins
(27) of IC906. There are sampling hold blocks generated from
the SHP and SHD pulses, and it is here that CDS (correlated
double sampling) is carried out.
After passing through the CDS circuit, the signal passes
through the AGC amplifier (VGA: Variable Gain Amplifier). It
is A/D converted internally into a 10-bit signal, and is then
input to ASIC (IC101). The gain of the VGA amplifier is con-
trolled by pin (31)-(33) serial signal which is output from ASIC
(IC101).
CDS
PxGA
CCDIN
CLAMP
INTERNAL
CLOCKS
PRECISION
RG
HORIZONTAL
4
TIMING
DRIVERS
H1-H4
GENERATOR
HD
Fig. 1-4. IC906 Block Diagram
5. Lens drive block
5-1. Shutter drive
The shutter drive signal (SIN1 and SIN2) which is output from
the ASIC expansion port (IC106) is drived the shutter constant
level driver (IC951), and then shutter plunger is opened and
closed.
5-2. Iris drive
The iris stepping motor drive signals (IIN1 and IIN2) which are
output from the ASIC (IC101) are used to drive by the motor
driver (IC951).
5-3. Focus drive
The focus stepping motor drive signals (FIN1, FIN2, FIN3 and
FIN4) which are output from the ASIC (IC101) are used to
drive by the motor driver (IC951). Detection of the standard
focusing positions is carried out by means of the
photointerruptor (FPI-E) inside the lens block.
5-4. Zoom drive
The zoom DC motor drive signals (ZIN1 and ZIN2) which are
output from the ASIC (IC101) are used to drive by the motor
driver (IC951). Detection of the zoom positions is carried out
by means of photoreflector (ZPI-E) inside the lens block.
VRT
VRB
VREF
2~36 dB
10
DOUT
VGA
ADC
CLAMP
CLI
CORE
SYNC
INTERNAL
REGISTERS
VD
SL
SCK
SDATA
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