Diagrams - Sony PCM-D50 Service Manual

PCM-D50
THIS NOTE IS COMMON FOR PRINTED WIRING BOARDS AND SCHEMATIC DIAGRAMS.
(In addition to this, the necessary note is printed in each block.)
For Printed Wiring Boards.
Note:
•
: Parts extracted from the component side.
•
: Pattern from the side which enables seeing.
(The other layers' patterns are not indicated.)
Caution:
Pattern face side: Parts on the pattern face side seen from
(SIDE B) the pattern face are indicated.
Parts face side: Parts on the parts face side seen from
(SIDE A) the parts face are indicated.
• Lead layouts
Lead layout of conventional IC
18
SECTION 4

DIAGRAMS

surface
CSP (Chip Size Package)
For Schematic Diagrams.
Note:
• All capacitors are in F unless otherwise noted. (p: pF)
50 WV or less are not indicated except for electrolytics
and tantalums.
• All resistors are in
1
and / W or less unless otherwise
4
specifi ed.
•
: internal component.
•
: panel designation.
Note: Note:
Les composants identifi és
The components identi-
fi ed by mark
or dotted par une marque
line with mark are criti- critiques pour la sécurité.
cal for safety. Ne les remplacer que par
Replace only with part une piéce portant le nu-
méro spécifi é.
number specifi ed.
•
: B+ Line.
•
: B– Line.
• Power voltage is dc 6.0V and fed with regulated dc power
supply from battery terminal.
• Voltages and waveforms are dc with respect to ground
under no-signal (detuned) conditions.
no mark : PB
[ ] : REC
: Impossible to measure
• Voltages are taken with a VOM (Input impedance 10 M ).
Voltage variations may be noted due to normal production
tolerances.
• Waveforms are taken with a oscilloscope.
Voltage variations may be noted due to normal production
tolerances.
• Circled numbers refer to waveforms.
• Signal path.
: REC (DIGITAL)
: REC (ANALOG)
: PB (DIGITAL)
: PB (ANALOG)
• The voltage and waveform of CSP (chip size package)
cannot be measured, because its lead layout is different
from that of conventional IC.
sont