Ic Block Diagram - Sanyo MCD-S870F Service Manual

i
IC BLOCK DIAGRAM & DESCRIPTION
IC101 LA922CIMS (Servo Signal Processor)
No. PIN NAME III 01 FUNCTION
1 FIN2
I Connection Pin for Photo Diode of Pickup.
2 I FIN1 I I I FIN2+FIN1 =RF. FIN2-FIN1 = FE
3E 1:1
Connection Pin for Photo Diode of Pickup.
4F E-F=TE
5
I TB
1'1
Input Pm for DC ingredient of TE Signal.
6 TE- ] Connection Pin for Gain Setting Resistor of TE
I I
I Signal to TE Signal pin.
7 ! TE
O I Outout Pin for Trackina Error Sianal .
8 I TESI [ I I Input Pin for Track Error Sense Comparator. TE
[
I Signal through Band pass, and Inputted.
9
I
Scl I
frmut Pin for Shock Detection.
10 TH :1
Connection Pin for Time Constant Setting of
Tracking Gain.
11 TA
o
Output Pin for TA Amplifer.
12 TD- 1 Connection Pin for Constant of Tracking Phase
Compensation, Consist of
between
TD and VR.
13 TD
I Connection Pin for Constant of Tracking Phase
Compensation.
14 JP I
Connection Pin for Amplitude Setting of Track-
ing Jump (Kick Pulse) Signal.
15 TO
o
Output Pin for Tracking Control Signal.
16 FD
I
o
Outout Pin for Focusina Controf Sional.
17 FD-
1 Connection Pin for Constant of Focusing Phase
Compensation, Consist of between FD and FA.
18
FA +
I Connection Pin for Constant of Focusing Phase
Compensation, Consist of between FD- and
FA-.
19 FA- 1 Connection Pin for Constant of Focusing Phase
Compensation. Consist of between FA and FE.
20 I FE
I O I Output Pin for Focusing Error Signal .
,
21 FE-
f I Connection Pin for Gain Setting Resistor of FE ~
I
~ I Sional to FE Sional crin.
22 AGND ~-
Ground for Analog Signal.
23 SP
o Output Pin for Single End of Input Signal of the
CV +, CV- Pin.
24 I SPI I I I Inout Pin for SDindle Amohfier. I
25 SPG II
I
Connection Pin for Gain Setting Resistor, when
Scrindle 12 cm Mode.
I
26 I SP-
I I ] Connection Pin for Constant of Spindle Phase I
I
] Compensation with SPD Pin.
27 I SPD
~ t OutDut pin fOr SDindle
COntrOl
Sicrna!.
28 / SLEQ I I I Ccmne t"
c Ion Pin for Constant of Sled Phase I
Compensation.
29
SLD
o Output Pin for Sled Control Signal.
30
SL-
1 fnput Pin for Sled Signal from Micro Processor.
31 I SL+
I
f
32 JP- 1 Input Pin for Tracking Jump Signal from Digital
33]JP+ I I
I
Sional Processor.
I
34 TGL I
Input Pin for Tracking Gain Control Signaf from
Diaital Sianal Processor. TGL = H: Gain Low
~
Input Pin for Tracking Off Control Signal from
Digital Signal Processor. TOFF = H: Off
Outpul Pin for Track Error Sense Signal to
Diaital Sional Processor.
37 I HFL I I I High
Fr equency Level Signal use Detection
Main-Beam Position m on the pit or mirror.
38 I SLOF I I Inout Pin for Sled Servo Off Control.
39 ]
cv- I
f I fnput P'm for Constant Linear Velocmy Error
40 I Cv+
f I Signal from Digital Signal Processor.
41 RFSM
I
O I Output Pin for RF Signal.
42 I RFS- 1'1 Connection Pin for Gain Setting of RF and
Constant Setting of 3T Compensation of the
EFM Signal with RFSM Pin.
43 SLC
o
Slice Level Control Signal is Output Pin, It
I
I I Controf Level of Data-Slice by Digital Signal
Processor of the RF Waveform.
44 I SLI
I Input Pin for Level Control of Data-Slice by
I I
I Dioital Sional Processor,
45 ] DGND I - I Ground for Digital Signal.
46
I vc-
I
f fnput Pin For VCO Control Amplifier, Consist
I
I I of pLL LOOP Filter with VCOC and PDO of
Digital Signaf Processor.
47
Vcoc
o
Output Pin for VCO Control Signal.
48
Vco
o
OutDut Pin for VCO Sional.
49
DEF
o
Output Pin for Defect Detection of Disc.
50 CLK I fnput Pin for Reference Clock Pulse, Input
4.23 MHz of Digital Signal Processor.
51 CL I Input Pin of Clock Pulse for Command from
Micro Processor.
52 DAT
I Input Pin of Data for Command from Micro
Processor.
53 I CE I I I fnput Pin of Chip Enable for Command from
Micro Processor.
54 DRF
o
Detect RF Signal is Output Pin for RF Level
I I
I Detection.
55 LF I Connection Pin for Adjusting of VCO Free-run,
56 VCC2 -
VCC for Sewo and Digital Root.
57
REFI I
Bus Control Connection Pin for Reference
Voltage.
58 VR
o
Output Pin for Reference Voltage,
59 LF2 I Connection Pin for Time Constant Setting of
Defect Detection of the Disc.
60 PHI
1
Capacitor Connection Pin for Peak-hold of RF
Sianal.
61 I BH1 / I I Capac' Itor Connection Pin for Bottom-hold of i
I
I RF Signaf.
62 I LDD
o I
Output Pin of APC (Automatrc Power Control)
Circuit.
63 LDS I input Pin of APC (Automatic Power Control)
Circuit.
64 I VCC1 I I I VCC for RF Root I
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