Panasonic TC-P42GT30A Service Manual page 57

12.15. A Board Schematic Diagram - (13/20)
NONUSE_PIN
TS INPUT
PORT
PEAKS-LDA3 PEAKS-LDA3
TP8828
PORT00 P_PORT00
*R8843 47k
PORT01
PORTxx P_HS0BCLKIN R8858
C
PORT02 P_PORT02
10k C
P_HS0DIN0
PORTxx PORT03 P_PORT03
P_HS0DIN1
PORTxx PORT04 P_PORT04
PORTxx P_HS0DIN2 PORT05
P_HS0DIN3 PORT06
PORTxx
PORTxx P_HS0DIN4 PORT07
P_HS0DIN5
PORTxx PORT10 P_PORT10
P_HS0DIN6
PORTxx PORT11 P_PORT11
P_HS0DIN7
PORTxx PORT12
P_HS0SYNCIN
PORTxx PORT13 P_PORT13
PORTxx P_HS0VALIN PORT14 P_PORT14
PORT15 P_PORT15
*R8838
PORTxx P_HS1BCLKIN PORT16 P_PORT16
C
10k
PORT17 P_PORT17
PORT20
PORT21
PORT22
PORT23
TP8829
P_PORT24
PORT24
PORT25
PORT26 P_PORT26
PORT27 P_PORT27
PORT30 P_PORT30
PORT31
P_PORT32
PORT32
P_IS0CLK
PORTxx PORT33
PORTxx P_IS0PSYNC PORT34
P_IS0VAL
PORTxx
PORT36
P_IS0DATA
PORTxx
PORT37
PORT66 P_AGCR
PORT67
PORT73 P_PCCE2
PORT111
P_PCREG
PORT122
PORTxx P_PCDOE
PORTxx P_PCCE1
PORTxx P_PCWE
PORTxx P_PCOE
P_PCIOWR
PORTxx
P_PCIORD
PORTxx
PORTxx
PORTxx P_PCCD1
PORTxx
PORTxx
TS INPUT P_SBI1
PORT61
PORTxxx P_SBO1
PEAKS-LDA3
PORTxxx P_SBT1
P_TXD0
PORT165 P_RXD0
P_HSBCLKOUT
PORTxx
PORT167 P_RXD1
PORTxx P_HSDOUT0
PORTxx P_HSDOUT1
PORTxx P_HSDOUT2
PORTxx P_HSDOUT3
PORTxx P_HSDOUT4
PORTxx P_HSDOUT5
PORTxx P_HSDOUT6
PORTxx P_HSDOUT7
P_PCWAIT
PORTxx
PORTxx P_HSSYNCOUT
PORTxx P_PCCD1
P_HSVALOUT
PORTxx
PORTxx P_PCCD2
P_PCREADY
PORTxx
PORT111 P_PCVS1
XIRQ3
P_XIRQ3
XIRQ6 P_XIRQ6
XIRQ7 P_XIRQ7
XIRQ12 P_XIRQ12
P_STMSBI1
P14
P66 P_STMCECAVL1A
SMTRST P_STM5VDET3
Pxx
P_PCRESET
EA11 P_PORT37
EA8 P_PORT34
EA10 P_PORT36
EA9 P_PORT35
EA12 P_PORT20
EA13 P_PORT21
EA14 P_PORT22
EA15 P_PORT23
C
*R8438
EXB2HV103JV
IRQ
STM
PEAKS-LDA3 PEAKS-SLDA3
XIRQ3 P_XIRQ3
XIRQ4 P_XIRQ4
XIRQ5 P_XIRQ5
XIRQ6 P_XIRQ6
XIRQ7 P_XIRQ7
XIRQ8 P_XIRQ8
Pxx P_STMHPDO3
XIRQ9 P_XIRQ9 P_STM5VDET3
Pxx
XIRQ10 P_XIRQ10
XIRQ11 P_XIRQ11 C
XIRQ12 P_XIRQ12
Pxx P_STMGPIO4
DMD
R8836
PEAKS-LDA3
PA1
C
1k
P_RFAGC R8837
PA4
C
P_BSIQ_I
1k
P_BSIQ_Q
POWER
TS
PEAKS-LDA3
PEAKS-LDA3
VJ8814
SUB3.3V
VJUMP1005-P
P_VREF5V
USB
SUB3.3V
PEAKS-LDA3
VJ8839
TCON2.5V
P
USB
PEAKS-LDA3
ACHIP
P_PWM1LP
Pxx
PEAKS-LDA3
P_PWM1LN
Pxx
P_PWM1RP
Pxx
P_FBL1_RFAGC2
P_PWM1RN
Pxx
P_V1
SUB3.3V
LVDS REF
GUARD
P_LVDSRREF
R8847
24k
RL=50 :22k 30k
LVVSS RL=100 :24k 30k
C
C
SATA REF
GUARD
P_SATAREF
GT:USE
VT:NON USE R8848
0.5%
6.2k
1%
AVSSSATA
C
TS_INPUT
DEBUG_I2S
PEAKS-SLD2
PEAKS-LDA3
ABCKO
P_PORT13
ALRCKO
P_PORT14
ASDOUT0
P_PORT30
ASMCK
P_PORT31
C
INITHAL_SETUP
SUB3.3V
STB3.3V 11/29 R8856
SUB3.3V STB3.3V
N088-0289
XTALSEL1
P_XTALSEL1
XTALSEL0
P_XTALSEL0
bootstm
P_MAINPWRON
bootstm
P_DDRPWRON
boot_mode_sel[3]
P_EA24
boot_mode_sel[2]
P_NFCLE
boot_mode_sel[1]
P_PORT05
boot_mode_sel[0]
P_PORT06
clk_mode[4]
P_TXD0
clk_mode[3]
P_XNFRE
clk_mode[2]
P_XNFCE
clk_mode[1] P_ERXW
clk_mode[0]
P_NFALE
ed_pullup_sel
P_EAS
ea_pullup_sel
P_ECLK
BOOTBT P_XNFWE
SDBOOT
P_PORT07
eclk_mode[1]
P_XEWE1
eclk_mode[0] P_XEWE0
mode_sel_soft
P_TXD1
rev0_init P_IECOUT
rsv1_init
P_RMCO
cputest_sg
P_XERE
C
DDR_POWER_CTRL
P_DDR3PWRCTL
57
P_IS0PSYNC CHPSYNC0
P_IS0VAL CHVAL0
P_IS0CLK CHCLK0
SWIN
P_IS0DATA
CHDATA0
C
SATA
SATA/USB CLK(Reserve)
C8801
Main XTAL Select :
00=24.576MHz [Inner PD Resistance](reverse)
STM USE : 0=USE[Inner PU Resistance] C
C8800
10p 50V
DDR Hold Mode : 1=NOT USE[Internal PU Resistance]
BOOTMODE:
[COMMON] NAND-Flash 2kpage Bus wdth 8bit & retry block 8
0011:Inner ROM boot address 5 & 1bit ECC
0010:Inner ROM boot address 5 & 4bit ECC
0001:Inner ROM boot address 4 & 1bit ECC
0000:Inner ROM boot address 4 & 4bit ECC
[Premium] IPPLL Freqency change 0=800MHz, 1=600MHz[Inner PD Resistance]
VCXO Select: 0=Inner[Internal PU Resestance](reverse)
SATA/USB Reference clock select(reverse)
00 : USB: VPLL27, SATA: VPLL27[Internal PU resistance]
A2PLL ref clk : 0=AXO[Internal PD Resistance], 1=UPLL DIFFERENTIAL IMPEDANCE
100
ED PullUP:0=USE[Inner PD Resistance](reverse)
EA PullUP:0=NONUSE(reverse)
P_DTX
Addr/Data Mode : 0=ADMUX[Internal PU Resistance](reverse)
P_NDTX
Boot Mode : 1=SD, 0=NAND
ECLK Frequency Select
P_NDRX
2'b01 = 50MHz
2'b11 = Low Fix [Internal PU Resistance] P_DRX
DIFFERENTIAL IMPEDANCE
Reserve(reverse) 100
Reserve
Reserve
CPU Test Mode : 0=Normal [Internal PU Resistance (reverse)
P_SAMONI1
P_SAMONI2
TC-P42GT30A
24.576MHz
P_UXI
10p
50V
R8846
27k
C
P_UXO
X8800
H0J245500101
NX3225GA-EXS00A-CG01622-24.576MHZ