Main Assy (5/18) - Pioneer PDP-5016HD Service Manual

5

3.20.10 MAIN ASSY (5/18)

QQ
3 7 63 1515 0
• FLI8668 Flash Memory
T
OCMADDR[0..21]
4 /OCM_WE
4 /ROM_CS
4 /OCM_RE
4 OCMADDR[0..21]
TE
L 13942296513
R96:Delete
R98:Add
AMD Flash
SST Flash
Atmel
Flash
www
Flash
13Pin R95(000)
14Pin R97(103),R100(103)Open
.
15Pin R96(000),R460(000)Open
R98(000)Open,R113(103)
D08
5
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C57 C58 C59
10uF/16V/S 104p 104p
OCMADDR1
25
A0
OCMADDR2
24
A1
OCMADDR3
23
A2
OCMADDR4
22
A3
OCMADDR5
21
A4
OCMADDR6
20
A5
OCMADDR7
19
A6
OCMADDR8
18
A7
OCMADDR9
8
A8
OCMADDR10
7
A9
OCMADDR11
6
A10
OCMADDR12
5
A11
OCMADDR13
4
A12
OCMADDR14
3
A13
OCMADDR15
2
A14
OCMADDR16
1
A15
OCMADDR17
48
A16
OCMADDR18
17
A17
OCMADDR19
16
A18
OCMADDR20 R96 000
15
A19
OCMADDR21
10
A20
R98 OPEN_000
9
A21
11
WE
/ROM_CS /ROM_CS1
26
CE
R101 OPEN_000
28
OE
R460
OPEN-000
JP38
OCMADDR1
1 21
OCMADDR2
2 22
OCMADDR3
3 23
OCMADDR4
4 24
OCMADDR5
5 25
OCMADDR6
6 26
OCMADDR7
7 27
OCMADDR8
8 28
OCMADDR9
9 29
OCMADDR10
10 30
OCMADDR11
11 31
OCMADDR12
12 32
OCMADDR13
13 33
OCMADDR14
14 34
OCMADDR15
15 35
OCMADDR16
16 36
OCMADDR17
17 37
OCMADDR18
18 38
OCMADDR19
19 39
OCMADDR20
20 40
OPEN_52368-0401
4 OCMADDR[0..21]
OCMADDR0 R103
OCMADDR1
OCMADDR2
OCMADDR3
OCMADDR4
OCMADDR5
OCMADDR6
OCMADDR7
R104
OCMADDR8
OCMADDR10
OCMADDR11
OCMADDR12
OCMADDR9
OCMADDR13
OCMADDR14
OCMADDR15
OCMADDR16
R96:Add OCMADDR17
OCMADDR18
R98:Delete
OCMADDR19
OCMADDR20
OCMADDR18
ST Flash
SRAM
R95(000)Open
x ao
y
R97(103)Open,R100(103)
i
R96(000)Open,R460(000)
R98(000),R113(103)Open
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6
8
3V3_F 3V3STB
L2
BLM31PG601SN1
C60
104p
U11
M28W160CT-70N6E
OCMDATA0
29
D0
OCMDATA1
31
D1
OCMDATA2
33
D2
OCMDATA3
35
D3
OCMDATA4
38
D4
OCMDATA5
40
D5
OCMDATA6
42
D6
OCMDATA7
44
D7
OCMDATA8
30
D8
OCMDATA9
32
D9
OCMDATA10
34
D10
OCMDATA11
36
D11
OCMDATA12
39
D12
OCMDATA13
41
D13
OCMDATA14
43
D14
OCMDATA15
45
D15
3V3_F
47
VCCQ
R97 103
14
WP
R99 OPEN_103
12
RP
R594 000
R100
OPEN_103 C61
104p
OCMDATA[0..15] 4
OCMDATA0
OCMDATA1
OCMDATA2
OCMDATA3
OCMDATA4
OCMDATA5
OCMDATA6
Q Q
OCMDATA7
M_PE2
3 6 7 1 3
OCMDATA8
OCMDATA9
OCMDATA10
OCMDATA11
4 /ROM_CS
OCMDATA12
4 OCMADDR21
OCMDATA13
4 /OCM_CS1
OCMDATA14
OCMDATA15
/ROM_CS1
M_PE2
5VSTB
C666 104p
C667
10uF/16V/S
3V3_F
OPEN-103
1 8
PR33
2 7
103*4
3 6
4 5
4 5
PR34
3 6
103*4
2 7
1 8
OPEN-103
1 8
PR35
2 7
OPEN-103*4
3 6
4 5
R105 OPEN_103
R106 103
R107 103
R108 OPEN-103
R109 OPEN_103
R110 103
R111 OPEN-103
R112 103
R113 103
R114 103
R479 OPEN_103
u163
.
PDP-5016HD
6
7
2 9 9 4 2 8
OCMDATA[0..15] 4
/RESET 4
5VSTB 3V3STB
R584 R585
222/F 222/F
/ROM_CS1
Q28
M_PE2 KST4401
2
1 5 0 5 8 2 9 9 4
OCMADDR21
Boot Strap
6:0: I2C to JTAG bridge address or General use
0=After power on Reset, continue the boot up
using internal ROM
7:
1=Stay in IntRom without checking any DDC2Bi
channel.(Force Debug)
8: 0=Use DDCB2Bi Channel #0
1=Use DDCB2Bi Channel #1
0=Do not perform power on up code CRC
check
1=Perform power up code CRC check.
9:
If the CRC check did not match the one
stored in the XROM configure block, blink a
led at a rate of 2 second per blink.
12:10: For General Purpose use
000 = 20-bit address, 8-bit EXT I/F
15:
001 = 24-bit address, 8-bit EXT I/F
14:
010 = 20-bit address, 16-bit EXT I/F
13:
011 = 24-bit address, 16-bit EXT I/F(4MByte Flash)
[011]
1XX = OCM disabled, external parallel control
bus (testbench)
16: Open (Internal ROM on, and mapped to top 32K)
Close (Internal ROM off-boot from ext ROM)
18: 00 = I2C to JTAG Bridge disabled
m
17:
01 = ICD_SDA on VGA0_SDA, ICD_SCL on VGA0_SCL
10 = ICD_SDA on VGA1_SDA, ICD_SCL on VGA1-SCL
[01]
11 = I2C to JTAG bridge disabled, 5 JTAG signals mapped
co to AVS Pins
19: Open/0 (External Oscillator on TCLK pin)
Close/1 (XTAL and Internal Oscillator)
20: I2C to JTAG pull down
7
8
9 9
A
B
C
U
2 8 9 9
JP39
1
2
3
4
2mm
OPEN_79107-7001
D
E
F
D08
103
8