ViewSonic VG712s Service Manual page 26

gm5110/5120 System Design Example
4. LVDS (THC63LVDM83A)
The THC63LVDM83A transmitter converts 28 bits of CMOS/TTL data into LVDS (Low Voltage Differential Signaling)
data stream. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. The
HC63LVDM83A can be programmed for rising edge or falling edge clocks through a dedicated pin. The
THC63LVDF84A receiver converts the LVDS data streams back into 28 bits of CMOS/TTL data with falling edge
clock. At a transmit clock frequency of 85MHz, 24 bits of RGB data and 4 bits of LCD timing and control data
(HSYNC, VSYNC, CNTL1, CNTL2) are transmitted at a rate of 595 Mbps per LVDS data channel.
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ViewSonic Corporation VG712s/b
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