Architecture - FFV Q HD DVR Hardware Technical Reference Manual

A R C H I T E C T U R E
Q HD DVR
CIRCUIT BOARD

Architecture

The Q HD DVR
'
s primary design goal was to maintain video quality at a level suitable for use in
professional video applications. Since image quality is of utmost importance, JPEG2000
compression is used to provide the highest picture quality.
To support a sustained data rate at this level, the designers of the Q HD DVR included a SATA
hard disk controller on the circuit board.
The design includes an on-board ARM processor to oversee the hardware and to provide a
control interface through the serial ports.
All of the Q HD DVR's subsystems share thirty-two (32) megabytes of dynamic random access
memory. This memory is based on a true multi-port architecture that allows direct access by the
JPEG codec, the disk controller, and the local ARM processor. Direct access to this memory
permits each of the subsystems to perform to their maximum potential without concern for DMA
contention.
Following is a block diagram of the Q HD DVR.
Q HD DVR Hardware Technical Reference - Rev. 1.1
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