Dvi Input; Working Theorem - ViewSonic N2750w-1 Service Manual

7. Working Theorem

A. A/D converter (PC)
The ADC is to convert RGB analog signal to digital signal that scaling chip can acknowledge .The
AD9883 is a complete 8-bit 110 MSPS monolithic analog interface optimized for capturing RGB
graphic signal, a +3.3V power supply is necessary. Its 110 MSPS encode rate capability and
full-power analog Bandwidth 110 MHz supports display resolutions of up to 1280*1024 at 60 Hz.
A clamp signal is generated internally or may be provided through the CLAMP input pin .This
device is fully programmable via a two-wire serial port.
The HSYNC input receives a logic signal and provide the frequency reference for pixel clock
generation.
The clock generator COAST input may be used to stop synchronizing with HSYNC and continue
producing a clock at its present frequency and phase .
The CLAMP logic input may be used to define the time during which the input signal is clamped
to GND , establishing a black reference.
When the Power Down control input is bringing to low, AD9883 is put into a very low power
dissipation mode ,all the output buffers are placed in a high-impedance state.
B. Video Decoder (video)
The t0956 is a hightly integrated NTSC,PAL,and SECAM video decoder support for high quality
LCD-TV video applications. With an embedded SDRAM controller, t0956 supports NTSC/PAL
chroma and luma separation using a 3-dimensional adaptive comb filter for reducing the
cross-luma and cross-chroma artifacts.The frame buffer is also usec for 3D noise reduction circuit
that resumes good visual quality when the input signal is a noisy video source
The three 9-bits 108-MSPS A/D converters in the t0956 chip can be used for digitalizing RGB
from PC or YPbPr component signals as well. Piior to each channel contains the AGC and
clamping circuits with paogrammable gain and offset. A total of 10 video input terminals can be
configured to combinations of RGB, YPbPr , CVBS, S-Video inputs. The component, composite,
or S-Video signals are sampled at a free-run external clock frequency(20~80 MHz). After the
video decoder processing, the video data was sent out with a line-locked alignment rate(27 MHz).
The t0956 comes with 128-pin QFP package.

DVI input

C.
The SiI169 Receiver uses PanelLink Digital technology to support HDTV and high-resolution
digital displays for DTV and PC applications. It features High-bandwidth Digital Content
Protection (HDCP) for secure delivery of high-definition video in consurmer electronics products.
The SiI160 comes with integrated,pre-programmed HDCP keys, greatly simplifying
manufacturing and providing the highest level of security. For improved sase of use, the SiI169 has
enhanced jitter tolerancd and low-power standby mode. PanelLink Digital technology is the
world's leading DVI solution
D. Scaling controller
The t0932 chip is a LCD-TV controller chip for color display up to SXGA or 1400*1050 wide
screen panel.It includes a 96/64-bits controller for frame rate conversion and 3D interlace-to
progressive video processing. It also supports non-linear scaling for 4:3 to/form 16:9 conversion,
flexible picture in video display, cinema to TV conversion, hue/saturation adjustment, and
advanced OSD system.
The t0932 chip is targeted for the applications of high-end LCD-TV. It will accept all HDTV video
signals for flat panel display. It comes with 336-pin and 316-pin BGA package.
ViewSonic Corporation
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