LG -C300 Service Manual page 28

3.2.7 External Reset Handling
The chip reset can be controlled by an external RESET_N ball. If this ball is pulled low, the chip will be
reset. All PMU registers are reset during the external reset including LSIM control bits. The PMU
statemachines are also not reset from the external reset. An SW or watchdog reset will not reset the PMU
registers. A SW and Watchdog reset is seen on the reset_n pad to allow the reset of external devices.
Basically there are three reset sources, first the reset signal controlled by the PMU (reset_pmu_n_o),
second the reset signal controlled by the SCU (resetout_o) and third the external reset (RESET_N). The
SCU reset is triggered by SW (for example due to a SW reset or watchdog reset). The PMU reset is
controlled by the PMU state machine. The output of the reset handling block is the reset_postscu_n_o
signal. This signal controls for example the C subsystem and releases reset for the controller. During
normal start up, the PMU releases the reset_pmu_n_o signal after entering the SYSTEM ON state. At this
time the resetout_o signal is high, the RESET_N pad is not pulled low and therefore the
reset_postscu_n_o signal follows the reset_pmu_n_o signal. That means the C reset will be released
and the C starts operation. If the SW triggers an external reset via the SCU, signal resetout_o will be
forced to low for a certain time and RESET_N will be forced to low by the open drain driver. At the same
time the feedback to the SCU will be masked to not reset the baseband. The RESET_N pad is in the
VDDRTC domain but the internal pull up is connected to the VDD_VDIG1 (1.8V) domain. That allows the
pad to be used as reset for external devices running in the VDD1V8 domain. The RESET_N pad can also be
used to monitor the chip internal reset condition during startup.
The open drain driver is a weak driver, that means it can be forced to high during debug from external
pushing some current into the pad. In testmode signal reset_pmu_n_o is high, that means the chip reset
is fully controlled from external .
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3. TECHNICAL BRIEF
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3. TECHNICAL BRIEF
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