Sony HCD-DZ370 Service Manual page 73

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3 7 63 1515 0
Pin No. Pin Name
53
54
55
56 to 62 HA2 to HA8
63, 64 HA18, HA19
65
66
67 to 74 HA16 to HA9
75
76 XROMCS
77
78
79, 80 HD0, HD1
81
82 to 86 HD2 to HD6
87
88 RESERVED
89
90
91, 92 HA17, HA0
93
94
95
96
97
TE
L 13942296513
98
99
100
101
102
103
104
105
106
107
108 xSYSRST
109 RESERVED
110
111
112
113 to 117
118
119 to 121 RD2 to RD0
122 to 129 RD15 to RD8
130
131
132
133
134
135
www
136
137, 138 BA0, BA1
139
.
140, 141 RA0, RA1
142
143, 144 RA2, RA3
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I/O
LIMITSW I LIMIT SW signal input
MSW O DVD/CD PD –VR select signal output
DVDD18 — Power supply (+1.8V)
O Flash ROM address bus A2 to A8 output
O Flash ROM address bus A18, A19 output
DVDD3 — Power supply (+3.3V)
XWR O Flash ROM write signal output
O Flash ROM address bus A16 to A9 output
HA20 Flash ROM address bus A20 output
O Flash ROM chip select signal output
HA1 O Flash ROM address bus A1 output
XRD O Flash ROM read signal output
I/O Flash ROM data bus D0, D1 input/output
DVSS — Ground terminal
I/O Flash ROM data bus D2 to D6 input/output
HA21 I/O Flash ROM data bus D21 input/output
— Not used (Open)
HD7 I/O Flash ROM data bus D7 input/output
DVSS — Ground terminal
O Flash ROM address bus A17, A0 output
DVDD18 O Flash ROM data bus D18 input/output
FWR O Loading motor control (FWR) signal output
REV O Loading motor control (REV) signal output
DVDD3 — Power supply (+3.3V)
IFSDO O CPU I/F serial data output
IFCK O CPU I/F serial clock output
xIFCS O CPU I/F chip select output
IFSDI I CPU I/F serial data input
SCL O EEPROM serial clock output
SDA I/O EEPROM serial data input/output
CKSW I Chuck/Tray detect switch signal input
OCSW I Chuck/Tray detect switch signal input
RXD I RXD signal input from Jig
TXD O TXD signal output to Jig
ICE O Not used (Open)
I System reset signal input
I Not used (Open)
xIFBSY I Busy signal input from CPU I/F
DQM0 O SDRAM lower byte mask signal output
EEWP I EEPROM ready/Busy wake up signal input
RD7 to 3 I/O SDROM data bus D7 to D3 input/output
DVDD3 — Power supply (+3.3V)
I/O SDROM data bus D2 to D0 input/output
I/O SDROM data bus D15 to D8 input/output
TSD_M I TSD signal input
DVDD3 — Power supply (+3.3V)
DQM1 O SDRAM lower byte mask signal output
_RWE O SDRAM write enable signal output
_CAS O SDRAM column address strobe signal output
_RAS O SDRAM row address strobe signal output
_RCS O SDRAM chip select signal output
x ao
y
O SDRAM bank address 0, 1 output
RA10 O SDRAM address bus A10 output
i
O SDRAM address bus A0, A1 output
DVDD18 — Power supply (+1.8V)
O SDRAM address bus A0, A3 output
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HCD-DZ370/DZ560/DZ570/DZ660/DZ777
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