Iic Or I 2 C Bus; Data Format - Sony CPD-G400 Training Manual

IIC or I
Overview
In recent years Sony monitors, television and other Sony and non-Sony
consumer products have switched over to a communications bus that has
more advantages than disadvantages. The major advantages are:
•
One less communications line (no latch, strobe, enable, acknowledge,
or chip select line).
•
As part of the CPU program, the number of slave IC on the bus is
reconfirmed each time at start up (after CPU reset).
•
Bi-directional data is commonplace, but unidirectional is possible for
drivers.
•
Eliminates the need for two communications buses in complicated
products.
•
Communications (data and clock) are always present as long as the
set is ON (active).
•
More than one master IC can be programmed into the fixed number of
ICs on the bus so one IC does not have to talk to the master to com-
municate with another IC.
Using this IIC communications format, only parallel data and clock lines
connect the ICs. Instead of singling out a slave IC using individual chip
select lines to communicate on the bus, the specific device is addressed
within the data.
This format makes monitor adjustments possible from an external device
using DAS software. The connection to the IIC bus via a connector on the
board is usually near the CPU.

Data Format

The IIC bus has several parts:
•
Start Bit
•
Slave Address
2 C Bus
•
Read/Write Bit
•
Several Acknowledge Bits
•
The Data
•
Stop Bit
Start Slave
bit Address
Data Ack
Start / Stop Bit
Each device on the IIC bus must be able to recognize its own address.
The beginning of any data transfer is a "start bit". The start bit has no
clock pulse. Any time the data lines falls from HIGH to LOW independent
on the clock line (usually HIGH), all devices on the bus will begin loading
in the data on the bus. The stop bit is conversely a LOW to HIGH transi-
tion from the master IC.
Slave Address
The address word consists of a seven bits of an eight-bit word. (Current
technology digital communication is often in 8, 16 or 18 bit words). This
address identifies the device that this data is for.
Read/Write Bit
The eighth bit of the address word is the direction read/write bit. It is
HIGH to accept the pending data for reading and LOW for WRITE into the
addressed IC.
Acknowledge Bit
Following the address from the master IC is an acknowledgement from
the destination IC. At this time the master IC's tri state data output will
switch to a high impedance input. As the pull up resistors on the data line
bring this line HIGH, the destination IC grounds this line at this time in the
clock cycle to indicate an acknowledgement of the address (or data) and
verify the presence of the destination IC.
ii
Data Structure
Ack Data Ack Data
Read (H)
Write (L)
Data Ack Stop bit