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IC BLOCK DIAGRAM & DESCRIPTION
IC818 SST39VF800A-70-4C-EK(Flash Memory)
Memory Address
Symbol
AMS
-A
1
0
DQ
-DQ
15
0
CE#
OE#
WE#
V
DD
V
SS
NC
IC850 PQ2L2182MS(regulater)
1
CONTROL
3
IC852 PQ1X501M2Z(Regulater)
DC input : Vin
1
GND
2
CONTROL
3
ON/OFF control : Vc
X-Decoder
Address Buffer
& Latches
CE#
OE#
Control Logic
WE#
Pin Name
Function
Address Inputs
To provide memory addresses. During Sector-Erase A
lines will select the sector. During Block-Erase A
select the block.
Data Input/output
To output data during Read Cycles and receive input data during Write
Cycles.
Data is internally latched during a Write Cycle.
The outputs are in tri-state when OE# or CE# is high.
Chip Enable
To activate the device when CE# is low.
Output Enable
To gate the data output buffers.
Write Enable
To control the Write operations.
Power Supply
To provide power supply voltage:
Ground
No connection
Unconnected pins
2
DC output : Vo
5
4
Noise reduction : Nr
SuperFlash
Memory
Y-Decoder
I/O Buffer and Data
Latches
DQ
-DQ
15
0
MS
-A
MS
15
3.0-3.6V for SST39LF200A/400A/800A
2.7-3.6V for SST39LF200A/400A/800A
IC851 PQ070XZ01Z(Regulater)
5
4
1
Pin No.
Symbols
1
Vin
DC INPUT
2
Vc
ON/OFF CONTROL
3
Vo
DC OUTPUT
4
Vadj
OUTPUT VOLTAGE ADJUSTMENT
5
GND
- 22 -
-A
address
11
address lines will
2
3
4
5
Description
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