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IC BLOCK DIAGRAM & DESCRIPTION
IC501 AK4352(2V & Low Power Multi Bit)
DID0
6
LRCK
5
Serial Input
3
BICK
Interface
SDATA
4
VDD
10
VSS
9
De-emphasis
PD
2
Control
TE
L 13942296513
No.
Pin Name
1
MCLK
2
PD
3
BICK
4
SDATA
5
LRCK
6
DIF0
7
DIF1
8
DEM
9
VSS
10
VDD
11
VREF
12
VCMR
www
13
AOUTR
14
AOUTL
15
VCML
.
16
CKS
Note: All input pins should not be left floating.
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DIF1
7
8X
Interpolator
8X
Interpolator
Clock Divider
8
1
DEM
MCLK
I/O
Function
I
Master Clock Pin
I
Power-Down Pin
When at "L", the AK4352 is power-down mode and is held in reset.
The AK4352 should always be reset upon power-up.
I
Serial Bit Input Clock Pin
This clock is used to latch audio data.
I
Audio Data Input Pin
I
L/R Clock Pin
This input determines which audio channel is currently being input on
SDATA
pin.
I
Digital Input Format Pin
I
These pins select one of four input modes.
I
De-emphasis Enable Pin
When at "H", de-emphasis of fs=44.1kHz is enabled.
-
Ground Pin
-
Power Supply Pin
I
Reference Voltage Input Pin
Normally connected to VDD.
O
Rch Comrnon Voltage Pin
O
Rch Analog Output Pin
O
Lch Analog Output Pin
x
ao
y
O
Lch Common Voltage Pin
i
I
Master Clock Select Pin
"L": 256fs
"H": 384fs
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8
16
CKS
Q Q
3
6 7
1 3
u163
.
- 5 -
2 9
9 4
2 8
15 VCML
14 AOUTL
LPF
13 AOUTR
LPF
12 VCMR
11
VREF
1 5
0 5
8
2 9
9 4
m
co
9 9
2 8
9 9
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