PREFACE INTRODUCTION This unit has DVD play function and hard disc videotape function. Under DVD PLAY mode, you can play all kinds of disc; under TV mode, you can receive TV programs, under AV mode, you can receive programs from exterior signal resources. In these mode above, you can press the key of REC to videotape program;...
GENERAL INFORMATION FRONT PANEL STANDBY/ON DISC TRAY When loading a disc, place disc in the Press to switch the player on/off Displays information on the disc tray with the label side facing up status of the DVR STANDBY INDICATOR LIGHT OPEN/CLOSE button INFRARED SENSOR Turn on in red when standby, otherwise...
GENERAL INFORMATION REMOTE CONTROL STANDBY/ON button Switch between standby and working status TITLE button Show the title of disk. When activated, allows the user to select the desired title for playback DISPLAY button Open/Close the screen display NUMBER buttons Number selection REPEAT button Repeat playback A-B button...
BLOCK DIAGRAM ~110~240V VIDEO OUT VIDIO IN PUT AUDIO OUT AUDIO IN PUT TUNER75 IN PUT +12V S-VIDEO OUT CB.CR.YOU T -12V POWER COAXIAL OUT BOARD OPTICAL OUT AV BOARD +3.3V +2.5V +1.8V DVD LOADER MAIN BOARD DRIVE MPEG VIDEO DECODER& MPEG-2 AUDIO/ VIDEO CODER 40GB HDD...
Circuit Diagram: ICE2AXXX for OFF ¨C Line Switch Mode Power Supplies...
Page 10
ICE2AXXX for OFF – Line Switch Mode Power Supplies Protection Functions The block diagram displayed in Fig. 4 shows the interal functions of the protection unit. The comparators C1, C2, C3 and C4 compare the soft-start and feedback-pin voltages. Logic gates connected to the comparator outputs ensure the combination of the signals and enables the setting of the “Error-Latch”.
Page 11
ICE2AXXX for OFF – Line Switch Mode Power Supplies Overload and Open-Loop Protection • Feedback voltage (VFB) exceeds 4.8V and soft start voltage (VSS) is above 5.3V (soft start is completed) (t1) • After a 5µs delay the CoolMOS is switched off (t2) •...
Page 12
ICE2AXXX for OFF – Line Switch Mode Power Supplies References Keith Billings, Switch Mode Power Supply Handbook Ralph E. Tarter, Solid-State Power Conversion Handbook R. D. Middlebrook and Slobodan Cuk, Advances in Switched-Mode Power Conversion Herfurth Michael, Ansteuerschaltungen für getaktete Stromversorgungen mit Erstellung eines linearisierten Signalflußplans zur Dimensionierung der Regelung Herfurth Michael, Topologie, Übertragungsverhalten und Dimensionierung häufig eingesetzter...
CS98000 Internet DVD (iDVD) Chip Solution Features Description Powerful Dual 32-bit RISCs >160MIPS Overall the CS98000 Crystal DVD Processor is targeted as a market specific consumer entertainment processor Software based on popular RTOS, C/C++ empowering new product classes with the inclusion of a MPEG video decoder supports DVD, VCD, DVD player as a fundamental feature.
Page 15
CS98000 Pin Assignments pins. For some signal pins, a secondary function and direction are also shown. For pins having more Table 6 lists the pin number, pin name and pin type than one function, the primary function is chosen for the 208 pin CS98000 package. The primary when the chip is reset.
EM638165 Pin Descriptions Table 1. Pin Details of EM638165 Symbol Type Description Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal.
Page 22
EM638165 Pin Descriptions Table 1. Pin Details of EM638165 Symbol Type Description Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. Input Clock Enable: CKE activates(HIGH) and deactivates(LOW) the CLK signal.
EM638165 Operation Mode Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows the truth table for the operation commands. Table 2. Truth Table (Note (1), (2) ) Command State DQM BA CS# RAS# CAS# WE# 0-9,11 BankActivate...
Page 24
EM638165 Commands BankActivate (RAS# = "L", CAS# = "H", WE# = "H", BAs = Bank, A0-A11 = Row Address) The BankActivate command activates the idle bank designated by the BA0,1 signals. By latching the row address on A0 to A11 at the time of this command, the selected row access is initiated.
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc.
Page 34
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK Overview The CS92288 is a real time MPEG-2 audio/video encoder and decoder (CODEC), with system multiplexor/demultiplexor and on-screen display (OSD). For video coding, the CS92288 fully complies with the ISO/IEC 13818 Main Level @ Main Profile (ML@MP) or with the ISO/IEC 11172 (MPEG-1) formats.
Page 35
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK – Constant Bit Rate Support: up to 15Mbps (IPB frames) and 30Mbps (I frame only) – Variable Bit Rate Support: • Real-time one-pass rate control • User-selectable average bitrate – Proprietary High Performance Motion Estimation Engine •...
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK – Glueless interface to industry standard SDRAM(s) – Glueless interface to Data Flash and EPROM memories – 8051 Protocol interface – I – General Purposed I/O – Glueless interface to USB controllers – Programmable clock output for audio A/D and D/A converters. •...
Page 37
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK Optional Firmware EPROM or Flash Video In NTSC/PAL Decoder YC/CV Video In Video Out NTSC/PAL CS92288 64-bit Video Out SDRAM MPEG-2 A/V Encoder Controller YC/CV SDRAM CODEC Audio I/O Audio In Host Interface Audio Out Drive Front CD-R/W...
Page 38
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK All blocks inter-communicate with two major data buses: a 64-bit wide data bus (D-Bus) and a 16-bit wide register bus (R- Bus). The PLL block is used to multiply (4X) the SYSCLK frequency to provide for all internal blocks and external memory clocking.
Page 39
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK be done in the most efficient way. The VOU can perform a variety of postprocessing operations, including horizontal and vertical scaling, telecine, and video format conversion. The OSD block mixes text and/or graphics from the OSD buffer (in SDRAM) with the output of the VOU and generates a cor- rectly sequenced ITU-R BT.601 or 656 4:2:2 output video stream.
Page 40
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK directly by the OSD unit, where it can be mixed with OSD data. The output of the OSD unit is passed back to the VIU and then to SDRAM for video encoding. As in the previous mode, additional preprocessing of the video data by the VPU may also be enabled.
Page 41
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK The RISC Microcontroller This is an embedded, programmable,32-bit ARC RISC processor. It performs multiplexing and demultiplexing of MPEG pro- gram streams and acts as a central sequencer. Its microcode can be downloaded either from an external host, from external data Flash, or from an external EEPROM, through the Host Interface Unit.
Page 42
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK Signal Descriptions This section groups the signals according to the bus interface type. The convention for active-low signals is to apply an over- score to the signal name, e.g., active-low SIGNAL and active-high SIGNAL. Pin Types are defined as: I/O = Input and output; I = Input only;...
Page 43
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK Table 2: Video Interface HREF_MOD Horizontal Output Reference for ITU-R BT.601. Input in Slave mode; output in Master mode. High assertive VSYNC_DEM Vertical Input Sync for ITU-R BT.601. Low assertive VSYNC_MOD Vertical Output Sync for ITU-R BT.601. Input in Slave mode; output in Master mode.
Page 44
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK Table 5: Global Interface Pin Name Type Pin Number Function SYSCLK System Clock (27 MHz) HARD_RESET Chip Reset, low assertive (Pull-up Resistor Provided) PLL_RESET PLL Reset, low assertive. Pull high for normal operation. APLL_RESET Audio PLL Reset, low assertive.
Page 45
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK System Interfaces The system interfaces consists of Host, Video, Audio, Memory, and Global interfaces; their definitions are detailed as follows Host Interface The Host Interface Unit (HIU) port of the CS92288 provides an interface between the CS92288 on-chip CPU and components of an off-chip host system, such as boot ROM, Flash memory, or a host microcontroller.
Page 46
CS92288 MPEG-2 AUDIO/VIDEO CODEC DATA BOOK SYS_RDY is an active-high output System Ready signal to indicate HIU power-up properly and is ready for software down- load. GPIO[5:0] is an 6-bit bidirectional bus for general purpose I/O. After reset, these pins are configured as input only. After- wards, their function is programmable by microcode.
KRETON VT3617161 Jan., 1999 Description The VT3617161 is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V power supply. This SDRAM is delicately designed with performance concern for current high-speed applica- tion.
Page 49
KRETON VT3617161 Jan., 1999 Pin Configuration 50-Pin Plastic TSOP(II)(400 mil) DQ15 D Q 0 DQ14 DQ13 D Q 3 DQ12 DQ11 DQ10 SS Q LDQM UDQM (BS)A Pin Description (VT3617161) Pin Name Function Pin Name Function A0-A11 Address inputs LDQM, Lower DQ mask enable and - Row address A0-A10...
Page 50
KRETON VT3617161 Jan., 1999 B lock D iagram C L K C loc k G ene ra tor C K E A d dre ss R o w A d d res s B a n k B B u ffe r &...
Page 51
KRETON VT3617161 Jan., 1999 Absolute Maximum Ratings Parameter Symbol Value Unit Voltage on any pin relative to Vss -1.0 to +4.6 Supply voltage relative to Vss -1.0 to +4.6 Short circuit output current Power dissipation Operating temperature 0 to + 70 Storage temperature -55 to + 125 Recommended DC Operating Conditions...
Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC SAA7114H comb filter, VBI-data slicer and high performance scaler CONTENTS BOUNDARY SCAN TEST 10.1 Initialization of boundary scan circuit FEATURES 10.2 Device identification codes Video decoder LIMITING VALUES Video scaler THERMAL CHARACTERISTICS Vertical Blanking Interval (VBI) data decoder and slicer...
Page 53
Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC SAA7114H comb filter, VBI-data slicer and high performance scaler FEATURES Video decoder • Six analog inputs, internal analog source selectors, e.g. 6 × CVBS or (2 × Y/C and 2 × CVBS) or (1 × Y/C and 4 ×...
Page 54
Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC SAA7114H comb filter, VBI-data slicer and high performance scaler Digital I/O interfaces GENERAL DESCRIPTION • Real-time signal port (R port), inclusive continuous The SAA7114H is a video capture device for applications line-locked reference clock and real-time status at the image port of VGA controllers.
Page 56
Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC SAA7114H comb filter, VBI-data slicer and high performance scaler PINNING SYMBOL TYPE DESCRIPTION external digital pad supply voltage 1 (+3.3 V) DDD(EP1) test data output for boundary scan test; note 1 test data input for boundary scan test;...
Page 57
84H and 85H) IGPH multi purpose horizontal reference output signal; image port (controlled by subaddresses 84H and 85H) IPD7 to IPD4 54 to 57 image port data outputs internal digital core supply voltage 3 (+3.3 V) DDD(ICO3) IPD3 to IPD0...
Page 58
Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC SAA7114H comb filter, VBI-data slicer and high performance scaler SYMBOL TYPE DESCRIPTION TEST4 do not connect; reserved for future extensions and for testing: scan output TEST5 do not connect; reserved for future extensions and for testing: scan input XTRI X-port output control signal, affects all X-port pins (XPD7 to XPD0, XRH, XRV, XDQ and XCLK), enable and active polarity is under software control (bits XPE...
Page 59
Philips Semiconductors Preliminary specification PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC SAA7114H comb filter, VBI-data slicer and high performance scaler handbook, full pagewidth V DDD(EP1) V DDD(EP4) TEST2 TEST1 XTOUT HPD0 V SS(XTAL) HPD1 XTALO HPD2 XTALI HPD3 V DD(XTAL) V DDD(ICO4) V SSA2 HPD4 AI24...
PCF8563 Real time clock/calendar 1. General description The PCF8563 is a CMOS real time clock/calendar optimized for low power consumption. A programmable clock output, interrupt output and voltage-low detector are also provided. All address and data are transferred serially via a two-line bidirectional I C-bus.
Page 63
PCF8563 Philips Semiconductors Real time clock/calendar Block diagram CLKOUT CONTROL/STATUS 1 OSCI 1 Hz OSCILLATOR DIVIDER CONTROL/STATUS 2 32.768 kHz OSCO SECONDS/VL MINUTES HOURS V SS VOLTAGE DAYS DETECTOR WEEKDAYS V DD CONTROL MONTHS/CENTURY OSCILLATOR LOGIC MONITOR YEARS MINUTE ALARM HOUR ALARM DAY ALARM C-BUS...
PCF8563 Philips Semiconductors Real time clock/calendar handbook, halfpage V DD OSCI CLKOUT OSCO V SS PCF8563 MGR886 Fig 5. Device diode protection diagram. Pin description Table 3: Pin description Symbol Description OSCI oscillator input OSCO oscillator output interrupt output (open-drain; active LOW) ground serial data input and output serial clock input...
Product Description 5 W D U [ U V G O % Q P H K I W T C V K Q P & W C N & T K X G 5 W R R Q T V Two drives may be accessed via a common interface cable, using the same range of I/O addresses.
Need help?
Do you have a question about the 57 and is the answer not in the manual?
Questions and answers