Yamaha S80 Service Manual page 15

TC203C760HF-002 (XS725A00)
PIN
NAME I/O
NO.
1 Vss
2 CA0 I
3 CA1 I
4 CA2 I
5 CA3 I
6 CA4 I
7 CA5 I Address bus of internal register
8 CA6 I
9 CA7 I
10 CA8 I
11 CA9 I
12 CA10 I
13 CA11 I
14 VSS
15 CD0 I/O
16 CD1 I/O
17 CD2 I/O
18 CD3 I/O
19 CD4 I/O
20 CD5 I/O
21 CD6 I/O
22 CD7 I/O
23 CD8 I/O Data bus of internal register
24 CD9 I/O
25 CD10 I/O
26 CD11 I/O
27 CD12 I/O
28 CD13 I/O
29 CD14 I/O
30 VDD
31 VSS
32 CD15 I/O
33 CSN I Chip select
34 WRN I Write strobe
35 RDN I Read strobe
36 VDD
37 SYSH0 O
38 SYSH1 O
39 SYSH2 O
40 SYSH3 O NSYS/LNSYS upper 16 bits output
41 SYSH4 O
42 SYSH5 O
43 SYSH6 O
44 SYSH7 O
45 KONO0 O
46 KONO1 O Key on data
47 KONO2 O
48 KONO3 O
49 VSS
50 SYSL0 I/O
51 SYSL1 I/O
52 SYSL2 I/O
53 SYSL3 I/O NSYS input/LNSYS output lower 8 bits
54 SYSL4 I/O
55 SYSL5 I/O
56 SYSL6 I/O
57 SYSL7 I/O
58 KONI0 I
59 KONI1 I Key on data input
60 VDD I
61 VSS
62 KONI2 I
63 KONI3 I
64 DAC0 O DAC output
65 DAC1 O
66 WCLK O DAC0/DAC1 word clock
67 MELO0 O
68 MELO1 O
69 MELO2 O
70 MELO3 O MEL wave data output
71 MELO4 O
72 MELO5 O
73 MELO6 O
74 MELO7 O
75 VDD
76 ADLR O ADC word clock
77 MELI0 I
78 MELI1 I
79 MELI2 I
80 MELI3 I MEL wave data input
81 MELI4 I
82 MELI5 I
83 MELI6 I
84 MELI7 I
85 VSS
86 RCASN O DRAM column address strobe (RAS signal)
87 RA8 O
88 RA7 O
89 RA6 O
90 VDD
91 VSS
92 RA5 O DRAM address bus
93 RA4 O
94 RA3 O
95 RA2 O
96 RA1 O
97 RA0 O
98 RRASN O DRAM row address strobe (RAS signal)
99 RWEN O DARM write enable
100 VSS
101 RD7 I/O
102 RD6 I/O
103 RD5 I/O
104 RD4 I/O
105 RD3 I/O
106 RD2 I/O
107 RD1 I/O
108 RD0 I/O
109 VSS
110 RD17 I/O
111 RD16 I/O DRAM data bus
112 RD15 I/O
113 RD14 I/O
114 RD13 I/O
115 RD12 I/O
116 RD11 I/O
117 RD10 I/O
118 RD9 I/O
119 RD8 I/O
120 VDD
SWP30B AWM Tone Generator coped with MEG) Standard Wave Processor
PIN
FUNCTION
NO.
(Ground) 121
122
123
124
125
126
127
128
129
130
131
132
133
(Ground) 134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
(Power supply) 150
(Ground) 151
152
153
154
155
(Power supply) 156
157
158
159
160
161
162
163
164
165
166
167
168
(Ground) 169
170
171
172
173
174
175
176
177
178
179
(Power supply) 180
(Ground) 181
182
183
184
185
186
187
188
189
190
191
192
193
194
(Power supply) 195
196
197
198
199
200
201
202
203
204
(Ground) 205
206
207
208
209
(Power supply) 210
(Ground) 211
212
213
214
215
216
217
218
219
(Ground) 220
221
222
223
224
225
226
227
228
(Ground) 229
230
231
232
233
234
235
236
237
238
239
(Power supply) 240
NAME I/O
VSS (Ground)
HMD0 I/O
HMD1 I/O
HMD2 I/O
HMD3 I/O
HMD4 I/O
HMD5 I/O
HMD6 I/O Wave memory data bus (Upper 16 bits)
HMD7 I/O
HMD8 I/O
HMD9 I/O
HMD10 I/O
HMD11 I/O
HMD12 I/O
HMD13 I/O
HMD14 I/O
HMD15 I/O
VSS (Ground)
HMA0 O
HMA1 O
HMA2 O
HMA3 O
HMA4 O
HMA5 O
HMA6 O
HMA7 O
HMA8 O
HMA9 O
HMA10 O
VDD (Power supply)
VSS (Ground)
HMA11 O
HMA12 O Wave memory address bus
HMA13 O
HMA14 O
HMA15 O
HMA16 O
HMA17 O
HMA18 O
HMA19 O
HMA20 O
HMA21 O
HMA22 O
HMA23 O
HMA24 O
VSS (Ground)
MRASN O
RAS when DRAM(s) is connected to wave memory
MCASN O
CAS when DRAM(s) is connected to wave memory
MOEN O Wave memory output enable
MWEN O Wave memory write enable
VSS (Ground)
LMD0 I/O
LMD1 I/O
LMD2 I/O
LMD3 I/O
LMD4 I/O
LMD5 I/O
LMD6 I/O
LMD7 I/O Wave memory data bus (Lower 16 bits)
VDD (Power supply)
VSS (Ground)
LMD8 I/O
LMD9 I/O
LMD10 I/O
LMD11 I/O
LMD12 I/O
LMD13 I/O
LMD14 I/O
LMD15 I/O
VSS (Ground)
LMA0 O
LMA1 O
LMA2 O
LMA3 O
LMA4 O
LMA5 O
LMA6 O
LMA7 O
LMA8 O
LMA9 O
LMA10 O
LMA11 O
VSS (Ground)
LMA12 O
LMA13 O Wave memory address bus (Lower data memory)
LMA14 O
LMA15 O
LMA16 O
LMA17 O
VDD (Power supply)
VSS (Ground)
LMA18 O
LMA19 O
LMA20 O
LMA21 O
LMA22 O
LMA23 O
LMA24 O
VSS (Ground)
SYO O Sync. signal for master clock
SYOD O Sync. signal for HCLK/QCLK
QCLK O 1/12 master clock (64Fs)
HCLK O 1/6 master clock (128Fs)
CK256 O 1/3 master clock (256Fs)
SYSCLK O 1/2 master clock (384Fs)
VDD (Power supply)
SYI I Sync. clock
MCLKI I Master clock input
MCLKO O Master clock output
VDD (Power supply)
XIN I Crystal osc. input
XOUT O Crystal osc. output
VSS (Ground)
ICN I Initial clear
CHIP2 I 2 chips mode enable
SLAVE I Master/Slave select when 2 chips mode
TESTON I
ACIN I Test pin
DCTEST I
VDD (Power supply)
FUNCTION
S80
15