Sony AVD-S50 Service Manual page 27

Pin No. Pin Name
46 VDDE
47 WMD1
48 VSS
49 WMD0
50 PAGE2
51 VSS
52, 53 PAGE1, PAGE0
54 BOOT
55 BTACT
56 BST
57 MOD1
58 MOD0
59 EXLOCK
60 VDDI
61 VSS
62, 63 A17, A16
64 to 66 A15 to A13
67 GP10
68 GP9
69 GP8
70 VDDI
71 VSS
72 to 75 D15 to D12
76 VDDE
77 to 80 D11 to D8
81 VSS
82 to 85 A9, A12 to A10
86 TDO
87 TMS
88 XTRST
89 TCK
90 TDI
91 VSS
92 to 97 A8 to A3
98, 99 D7, D6
100 VDDI
101 VSS
102 to 105 D5 to D2
106 VDDE
107, 108 D1, D0
109, 110 A2, A1
111 VSS
112 A0
113 PM
114 SDI3
I/O
— Power supply terminal (+3.3 V)
I S-RAM wait mode setting terminal Fixed at "H" in this set
— Ground terminal
I S-RAM wait mode setting terminal Fixed at "L" in this set
O Page selection signal output terminal Not used. (Open)
— Ground terminal
O Page selection signal output terminal Not used. (Open)
I Boot mode control signal input terminal Not used. (Fixed at "L" in this set.)
O Boot mode state display signal output terminal Not used. (Open)
I Boot trap signal input from the system controller
PLL input frequency selection signal input terminal
I
"L": 384fs, "H": 256fs (fixed at "H" in this set)
Mode setting terminal
I
"L": single chip mode, "H": use prohibition (fixed at "L" in this set)
I PLL lock error and data error flag input from the digital audio interface IC
— Power supply terminal (+2.6 V)
— Ground terminal
O Address signal output terminal Not used. (Open)
O Address signal output to the S-RAM
O L/R sampling clock signal (44.1 kHz) output to the D/A converter and stream processor
O Decode signal output to the system controller
I Bit 1 input terminal of channel status from the digital audio interface IC
— Power supply terminal (+2.6 V)
— Ground terminal
I/O Two-way data bus with the S-RAM
— Power supply terminal (+3.3 V)
I/O Two-way data bus with the S-RAM
— Ground terminal
O Address signal output to the S-RAM
O Simple emulation data output terminal Not used. (Open)
I Simple emulation data input start/end detection signal input terminal Not used. (Open)
I Simple emulation asychronous break input terminal Not used. (Open)
I Simple emulation clock signal input terminal Not used. (Open)
I Simple emulation data input terminal Not used. (Open)
— Ground terminal
O Address signal output to the S-RAM
I/O Two-way data bus with the S-RAM
— Power supply terminal (+2.6 V)
— Ground terminal
I/O Two-way data bus with the S-RAM
— Power supply terminal (+3.3 V)
I/O Two-way data bus with the S-RAM
O Address signal output to the S-RAM
— Ground terminal
O Address signal output to the S-RAM
I PLL reset signal input from the system controller "L": reset
I Rear L-ch and R-ch audio serial data input from the digital audio processor
AVD-S50/S50ES
Pin Description
27