LG CRD-8402B Service Manual page 22

Pin No. Symbol
114 VSIO5
115 HDBD
116 HDB2
117 HDBC
118 HDB3
119 VDIO3
120 HDBB
121 HDB4
122 HDBA
123 HDB5
124 VSIO4
125 HDB9
126 HDB6
127 HDB8
128 HDB7
129 VDC3
130 XTL2
131 XTL1
132 VSC3
133 AVS3
134 PWM2N
135 PWM2P
136 AVD3
137 AVD4
138 XTLO
139 XTLI
140 AVS4
141 AVS5
142 PWM1P
143 PWM1N
144 AVD5
Notes :
• LRCK, BCK and PCMD are changed to 32-bit slot and 48-bit slot by command.
32-bit slot is output in 2's complements on an LSB-first basis and 48-bit slot is output in 2's complements on
an MSB-first basis.
• *'s signal is able to convert to output by a command. (Refer to sub CPU Register 08h (W) of decoder part)
• The GFS signal turns "H" upon coincidence between Frame Sync and the timing of interpolation protection.
XRAOF is a signal issued when a jitter margin of + 28F is exceeded by the 32K RAM.
•
• C2PO is a signal to indicate data error.
• XUGF is a negative Frame Sync pulse obtained from the EFM signal before Frame Sync protection is
effected.
18
I/O
Digital Power Supply GND
I/O 1,Z,0 Host Data Bus
I/O 1,Z,0 Host Data Bus
I/O 1,Z,0 Host Data Bus
I/O 1,Z,0 Host Data Bus
Digital Power Supply (3.3V)
I/O 1,Z,0 Host Data Bus
I/O 1,Z,0 Host Data Bus
I/O 1,Z,0 Host Data Bus
I/O 1,Z,0 Host Data Bus
Digital Power Supply GND
I/O 1,Z,0 Host Data Bus
I/O 1,Z,0 Host Data Bus
I/O 1,Z,0 Host Data Bus
I/O 1,Z,0 Host Data Bus
Digital Power Supply (2.5V)
O 1, 0 Crystal Oscillating Circuit Output of the Clock for Decoder
I Crystal Oscillating Circuit Input of the Clock for Decoder
Digital GND
Analog GND
O 1, 0 PWM Output of Audio DAC. Default R Ch, Reverse Phase
O 1, 0 PWM Output of Audio DAC. Default R Ch, Forward Phase
Analog Power Supply (2.5V)
Power Supply for Master Clock (2.5V)
O 1,0 Crystal Oscillating Circuit Output for the Master Clock
I Crystal Oscillating Circuit Input for the Master Clock
GND for the Master Clock
Analog GND
O 1, 0 PWM Output of Audio DAC. L Ch, Forward Phase
O 1, 0 PWM Output of Audio DAC. L Ch, Reverse Phase
Analog Power Supply (2.5V)
Description