Sanyo DC-TS750 Service Manual page 32

IC BLOCK DIAGRAM & DESCRIPTION
IC806 74VHCT08A (Quad 2-Input AND Gate)
1
A
0
B 2
0
3
O
0
A 4
1
5
B
1
O 6
1
7
GND
A
L
L
H
H
Pin Names
A B
n' N
O
N
IC818 LE28DW8163T (8Mbit Flash)
1
A15
2
A14
3
A13
4
A12
5
A11
6
A10
7
A9
8
A8
9
NC
10
NC
11
WE#
12
RESET#
13
NC
14
WP#
15
RY/BY#
16
A18
17
A17
18
A7
19
A6
20
A5
21
A4
22
A3
23
A2
24
A1
Symbols
A18,A17
A16-A0,A-1
A18-A15
A18-A10
DQ15-DQ0
CE#
OE#
WE#
BYTE#
RY/BY#
WP#
RESET#
VDD
VSS
14
V
CC
13 A
2
12 B
2
11 O
2
10 A
3
9 B
3
8 O
3
B O
L L
H L
L L
H H
Description
Inputs
Outputs
48 A16
47
BYTE#
CHARGE PUMP
46
VSS
&
45 DQ15/A-1
VOLTAGE
44
DQ7
REFERENCE
43
DQ14
CIRCUIT
42
DQ6
41
DQ13
40
DQ5
ADDRESS BUFFER
39
DQ12
38
DQ4
LATCH CIRCUIT
37 VDD
36
DQ11
35
DQ3
34 DQ10 A18-A0,A-1
33
DQ2
CE#
32
DQ9
OE#
31 DQ1
WE#
30
DQ8
WP#
29
DQ0
RY/BY#
28 OE#
RESET#
27
VSS
BYTE#
26
CE#
25
AD
Pin Name
Bank Selective Address Selects bank 1 when "L" and bank 2.
Flush Bank Address Sapply address for flush bank.
Flush Bank Block Address Select flush bank for erease.
Flush Bank Sector Sddress Select flush bank sector for erease.
To output data during read cycle and receive input data during write
Data Input/Output cycles. Data is internaliy latched during a writecycle. The output are
high inpedance when OE#,CE# is "H".
Chip Enable
To activate the flush bank when CE# is "L".
Output Enable
To activate the data output buffer .
Write Enable
To control the write, erease and program.
Bait Pin
Bait mode when "L" and word mode when "H".
Ladey/Beje Output
Output "L" when write and ezcept "H".
Write Protect
To activate hardware write protect when "L".
Reset
To activate hardware reset when "L".
Power Supply
2.7V~3.6V supply.
Ground
COLUMN DECODER
&
LOW DECODER
CONTROL LOGIC
Functions
- 33 -
128Kx16
or
256Kx8
FLUSH
BANK2
384Kx16
or
788Kx8
FLUSH
BANK1
DQ15-DQ0
IN/OUTPUT BUFFER
&
DATA LATCH