Sony STR-KS1000 Service Manual page 38

STR-KS1000
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• IC Pin Function Description
3 7 63 1515 0
MAIN BOARD IC1501 CXD9862R (DIGITAL AUDIO SIGNAL PROCESSOR)
Pin No. Pin Name
1 VSS
2
XRST
3
EXTIN
4
LRCKI3
5 VDDI
6
BCKI3
7
PLOCK
8
VSS
9 MCLK1
10
VDDI
11
VSS
12
MCLK2
13 MS
14 SCKOUT
15 LRCKI1
16 VDDE
17 BCKI1
18
SDI1
19
LRCKO
20
BCKO
21 VSS
22 TE KFSIO
L 13942296513
23 to 25 SDO1 to SDO3
26 SDO4
27 SPDIF
28
LRCKI2
29 BCKI2
30 SDI2
31 VSS
32 HACN
33 HDIN
34 HCLK
35 HDOUT
36 HCS
37 GP12
38 GP13
39 GP14
40 VDDI
41 VSS
42 GP15
43 OE0
44 CS0
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45 WE0
46 VDDE
47 WMD1
.
48 VSS
49 WMD0
50 PAGE2
38
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I/O
-
Ground terminal
I
System reset signal input from the system controller "L": reset
I
Master clock signal input terminal Not used
I
L/R sampling clock signal (44.1 kHz) input terminal Not used
- Power supply terminal (+1.8V)
I
Bit clock signal (2.8224 MHz) input terminal Not used
O
PLL lock signal output terminal Not used
-
Ground terminal
I System clock input terminal (13.9 MHz)
-
Power supply terminal (+1.8V)
-
Ground terminal
O
System clock output terminal (13.9 MHz)
I
Master/slave setting terminal "L": internal clock, "H": external clock Fixed at "L" in this set
O
Master clock signal output to the stream processor
I
L/R sampling clock signal (44.1 kHz) input from the digital audio interface receiver
-
Power supply terminal (+3.3V)
I Bit clock signal (2.8224 MHz) input from the digital audio interface receiver
I
Audio serial data input from the A/D converter
O
L/R sampling clock signal (44.1 kHz) output to the stream processor
O
Bit clock signal (2.8224 MHz) output to the stream processor
- Ground terminal
I
Audio clock signal input from the digital audio interface receiver
O
Audio serial data output to the stream processor
O
Audio serial data output terminal Not used
O SPDIF signal output terminal Not used
I
L/R sampling clock signal (44.1 kHz) input from the digital audio interface receiver
I
Bit clock signal (2.8224 MHz) input from the digital audio interface receiver
I
Audio serial data input from the digital audio interface receiver
- Ground terminal
O
Acknowledge signal output to the system controller
I
Serial data input from the system controller
I
Serial data transfer clock signal input from the system controller
O Serial data output to the system controller
I
Chip select input from the system controller
I
Write enable signal input from the system controller
O
SD-RAM chip enable output terminal Not used
O Row address strobe signal output terminal Not used
-
Power supply terminal (+1.8V)
-
Ground terminal
O
Column address strobe signal output terminal Not used
O
Output of data input/output mask to the S-RAM
O Chip select signal output to the S-RAM
O
Write enable signal output to the S-RAM
-
Power supply terminal (+3.3V)
x ao
y
I
External memory wait mode setting terminal Fixed at "H" in this set
i
- Ground terminal
I
External memory wait mode setting terminal Fixed at "H" in this set
O
External memory page selection signal output terminal Not used
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Description
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