Table of Contents
Advertisement
1. OUTLINE OF CIRCUIT DESCRIPTION
1-1. CA1 CIRCUIT DESCRIPTION
1. IC Configuration
IC901 (ICX488EQF) CCD imager
IC905 (H driver, CDS, AGC and A/D converter)
2. IC901 (CCD imager)
[Structure]
Interline type CCD image sensor
Image size
Pixels in total
Recording pixels
Pin No.
Symbol
Vø
1
6
2
Vø
5B
3
Vø
5A
4
Vø
4
5
Vø
3B
6
Vø
3A
7
Vø
2
8
Vø
1
9
Vø
ST
10
Vø
HLD
11
GND
12
GND
3. IC902, IC903 (V Driver) and IC905 (H driver)
An H driver and V driver are necessary in order to generate
the clocks (vertical transfer clock, horizontal transfer clock
and electronic shutter clock) which driver the CCD.
IC902 and IC903 are V driver. In addition the XV1-XV6 sig-
nals which are output from IC101 are the vertical transfer
clocks, and the XSG signal is superimposed at IC902 and
IC903 in order to generate a ternary pulse. In addition, the
XSUB signal which is output from IC101 is used as the sweep
pulse for the electronic shutter. A H driver is inside IC905,
and H1, H2 and RG clock are generated at IC905.
4. IC905 (CDS, AGC Circuit and A/D Converter)
The video signal which is output from the CCD is input to Pin
(27) of IC905. There are inside the sampling hold block, AGC
block and A/D converter block.
The setting of sampling phase and AGC amplifier is carried
out by serial data at Pin (32). The video signal is carried out
A/D converter, and is output by 12-bit.
Diagonal 6.67 mm (1/2.7 type)
2396 (H) x 1766 (V)
2288 (H) x 1712 (V)
Pin Description
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Horizontal addition control clock
Horizontal addition control clock
GND
GND
Table 1-1. CCD Pin Description
10
12
11
13
14
15
Fig. 1-1. CCD Block Diagram
Pin No.
Symbol
13
V
OUT
V
14
DD
øRG
15
16
Hø
1B
17
Hø
2B
18
GND
19
øSUB
20
C
SUB
21
Hø
1A
22
Hø
2A
23
GND
V
24
L
CDS
CCDIN
CLAMP
RG
HORIZONTAL
4
DRIVERS
H1-H4
Fig. 1-2. IC905 Block Diagram
– 2 –
7
6
4
3
2
9
8
5
B
Gb
B
Gb
Gr
R
Gr
R
B
Gb
B
Gb
Gr
R
Gr
R
B
Gb
B
Gb
Gr
Gr
R
R
B
Gb
B
Gb
Gr
R
Gr
R
B
Gb
B
Gb
(Note)
Gr
R
Gr
R
Horizontal register
17
18
16
19
20
21 22
23
(Note) :
Photo sensor
Pin Description
Signal output
Circuit power
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
GND
Substrate clock
Substrate bias
Horizontal register transfer clock
Horizontal register transfer clock
GND
Protection transistor bias
VRT
VRB
VREF
2~36 dB
10
PxGA
VGA
ADC
CLAMP
INTERNAL
CLOCKS
PRECISION
TIMING
CORE
SYNC
INTERNAL
GENERATOR
REGISTERS
SL
HD
VD
SCK
SDATA
1
24
DOUT
CLI
Hide quick links:
Advertisement
Table of Contents
