Main(Mda) Schematic Diagram - JVC GR-D370UC Schematic Diagrams

MAIN(MDA) SCHEMATIC DIAGRAM

DRUM_PG
DRUM_FG
DRUM_REF
C_FRB
TO CPU
CAP_FG
CAP_REF
LD_ON
L_FRB
MDA_PS
C1601
0.01
TO MAIN IF LOAD_FWD
(CN1601)
LOAD_REV
GND
D_FG-
D_PG-
D_PFG+
TO MAIN IF
COIL_COM
(CN1602)
D_COIL_U
D_COIL_V
D_COIL_W
GND
0 1
NOTES: 1. For the destination of each signal and further line connections that are cut off from this diagram, refer to "BOARD INTERCONNECTIONS".
2. The parts with marked ( ) is not used.
2-9(No.YF124)
R1630 0
R1631
0
C1607
0.047
D1602
OPEN
R1640 0
MAIN(MDA)
TL1612
TL1618
TL1613
TL1619
TL1617
D.COM
D.U
D.V
R1614 0.33
D.RNF
D.W
NC
L.FRB
L.REF
L.FWD
NC
L.GND
L.REV
L.VM
C.FGIN+
C1614
10µ /10
C.FGIN-
C.FGAMP
R1612
100K
R1613
1K TL1608
C1621
TL1605
1
R1622
10K
R1620
68K
TL1606
TL1609
C1606
0.0015
R1604
100K
D.PGIN-
D.PGAMP
D.PGSMT
C.HW-
C.HW+
C.HV-
C.HV+
IC1601
C.HU-
BD6637KV
C.HU+
NC
NC
C.W
C.RNF
C.V
C.U
NC
C1629
0.22
1 2 3
R1635
6 4
Q1601
UMC3N-W
C16
0.1
C16
10µ
R16
4.7K
3.3K
R1636
12K