Sony TA-DA9000ES Service Manual page 126

TA-DA9000ES
Pin No. Pin Name
VDD
61
VSS
62
DLDRI
63
64 CSWI
SLSRI
65
FLFRI
66
TEST3
67
CLK512
68
VSS
69
XRST
70
VDD
71
SCLK
72
XCS
73
SI
74
SO
75
DEXRI
76
DMLI
77
DMRI
78
79 VSS
80 PHAI
81 BCKAI
82 DQM
83 DLI
DRI
84
DCI
85
DLFEI
86
87 DLSI
DRSI
88
VSS
89
90 to 95 D15 to D10
96 VDD
97, 98 D9, D8
GND
99
100 D0
126
I/O
—
Power supply terminal (+3.3V)
—
Ground terminal
I
Surround back audio data input from the Dc cut digital filter
I Center and sub woofer audio data input from the Dc cut digital filter
I
Surround audio data input from the Dc cut digital filter
I
Front audio data input from the Dc cut digital filter
I
Input terminal for the test
I
Master clock signal input terminal
—
Ground terminal
I
Reset signal input terminal "L": reset
—
Power supply terminal (+3.3V)
I
Serial clock signal input from the main system controller
I
Chip select signal input from the main system controller
I
Serial data input from the main system controller
O
Serial data output to the main system controller
I
Not used
I
Data input terminal for L-ch down mix Not used
I
Data input terminal for R-ch down mix Not used
— Ground terminal
I
Clock signal input terminal Not used
I
Bit clock signal (2.8224 MHz) input terminal Not used
O
Not used
I Front L-ch data input terminal Not used
O
Front R-ch data input terminal Not used
O
Center data input terminal Not used
O
Sub woofer data input terminal Not used
O Surround L-ch data input terminal Not used
O
Surround R-ch data input terminal Not used
—
Ground terminal
I/O
Two-way data bus with the SD-RAM
— Power supply terminal (+3.3V)
I/O
Two-way data bus with the SD-RAM
—
Ground terminal
I/O
Two-way data bus with the SD-RAM
Description