Cache Protection - IBM Power 780 Technical Overview And Introduction

Advanced memory mirroring features
On the Power 770 server, the Advanced Memory Mirroring for Hypervisor function is an
optional chargeable feature. It must be selected in e-config.
On this server, the advanced memory mirroring is activated by entering an activation code
(also called Virtualization Technology Code, or VET) in the management console. If the
customer enables mirroring from the management console without entering the activation
code, the system boots only to standby and will wait for the customer to enter the VET code
(SRC A700474A displays). If mirroring was enabled by mistake, you must disable it and
power cycle the CEC, as mirroring state requires a CEC reboot to change. Hypervisor
mirroring is disabled by default on the Power 770 server.
On the Power 780 server, this feature is standard. There is no individual feature code in
e-config. The mirroring is enabled by default on the server.

4.2.5 Cache protection

POWER7+ processor-based systems are designed with cache protection mechanisms,
including cache-line delete in both L2 and L3 arrays, Processor Instruction Retry and
Alternate Processor Recovery protection on L1-I and L1-D, and redundant
L1-D, and L2 caches, and in L2 and L3 directories.
L1 instruction and data array protection
The POWER7+ processor's instruction and data caches are protected against intermittent
errors by using Processor Instruction Retry and against permanent errors by Alternate
Processor Recovery, both mentioned previously. L1 cache is divided into sets. POWER7+
processor can deallocate all but one set before doing a Processor Instruction Retry.
In addition, faults in the Segment Lookaside Buffer (SLB) array are recoverable by the
POWER Hypervisor. The SLB is used in the core to perform address translation calculations.
L2 and L3 array protection
The L2 and L3 caches in the POWER7+ processor are protected with double-bit detect
single-bit correct error detection code (ECC). Single-bit errors are corrected before being
forwarded to the processor and are subsequently written back to L2 and L3.
POWER7+ dramatically increases the size of the L3 cache: from 32 MB to 80 MB. Although
this larger cache can help deliver higher system performance, it also increases the potential
for encountering cache errors.
In addition, the caches maintain a cache-line delete capability. A threshold of correctable
errors detected on a cache line can result in the data in the cache line being purged and the
cache line removed from further operation without requiring a reboot. An ECC uncorrectable
error detected in the cache can also trigger a purge and deleting of the cache line. This
results in no loss of operation because an unmodified copy of the data can be held on system
memory to reload the cache line from main memory. Modified data is handled through Special
Uncorrectable Error handling.
L2-deleted and L3-deleted cache lines are marked for persistent deconfiguration on
subsequent system reboots until the processor card can be replaced.
In POWER7+ servers, the Power-On Reset Engine can dynamically (during run time) take the
chiplet containing the failing column offline and automatically substitute spare L3 capacity.
These servers can effectively self-heal the cache without causing an outage, reducing the
requirement to replace processors in the field because of predictive issues with the L3 cache.
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IBM Power 770 and 780 (9117-MMD, 9179-MHD) Technical Overview and Introduction
Repair
bits in L1-I,