Ic Block Diagram - Sanyo MCH-900F Service Manual

IC BLOCK DIAGRAM & DESCRIPTION
IC140 BA63SSFP ( POWER DRIVER)
/
I+R5
74
OP OUT
OP. AMP
35 OP IN (-) OP. AMP
36 OP IN(+)
OP. AMP
77
CH3-OUT A DRIVER CH3(-)
18 CH3-CJUT B
DRIvER CH3(+)
19
CH3-IN A DRIvER CH3
20 CH3-IN Er NOT USED
21
Vcc Vcc
22
Vcc Vcc
23
BIAS IN BIAS
24 CH4-IN B NOT USEO
25 CH4-IN A
DRIvER CH4
26 CH4-OUT B ORWER CH4 (+ )
27
CH4-OUT A ORIVER CH4(-)
28 GND GND
*
".
IC BLOCK DIAGRAM & DESCRIPTION
IC141 CXD2518Q ( DIGITAL SIGNAL PROCESSOR )
No.
Name 1/0
Description
,
.
[
No.
T SCOR o Turns "H- when sync SO or S1 m delecred.
41
2
SBSO
o serial OUtPul 01 sub-code P - W.
3
EXCK
I
42
Clock ,nput for reading SBSO.
4 S(X3O
o Serial output 01 SUBO & SOBIT.
43
5 SOCK r Clock mp.1 for reading SL3S0.
44
6 MUTE I "H" al mubng, "L" al mut,ng cancel. 45
7
SENS
o
SENS sgnal output to CPU.
46
8 XRST 1
System reset, "L- at ,esetfmg.
47
9 DATA
I
Inputs serial data from CPU.
48
Latches input from CPU.
10
49
XLAT I
Serial data latches at Ming edge.
50
11 CLOK I Inpuls serial data transfer clock from CPU.
51
12
Vss
-
GND.
52
13 SEIN I
Inputs SENS signal from SSP.
53
14
CNIN
I Inputs track jump count $ignal
54
15
DATO o
Outputs serial data to sSP
55
&H==+
Serial
data latches at lalhng edge.
O Oulputs serial data transrer clock 10 SSP.
PI" for TEST. Normal used state VDD.
=BEiE=a
interlace (or extenson
of M.
processor(oulput )
%44==2+
Used servo auto sequencer w,th SENS output.
ONIOFF control s!gna! {or spindle momr.
O Servo control signal for spindle motor.
E
56
57
58
59
60
61
62
E
63
64
65
I 27 LOCK o Not used
l16Li
28 TEST I
GND.
29 FILO o
' ' I
Output of falterfor master PLL. (Slave = O@al
67
PLL) 68
30 FILI rnpuls to filter for master PLL. 69
31 Pco o Outputs of charge pump for master PLL.
70
32
VOD -
Power supply for d!g4aL( + 5V) 71
33 AV=~l - Power supply Ior analog.
72
34 CLTV
I
VCO control voltage ,np"t for master PLL.
73
35 AVDD1 - Power supply for analog.( + 5v) 74
36 RF
EFM s,gnat mprt
75
37
Inputs constant cwfent for asymmetry correc-
76
BIAS I
hon C,rc"it.
77
38
Inputs compamtor voltage for asyrnmetiy cop
ASYI I
78
reCllOn CIICUIL
79
39 ASYO
o
EFM NI $wmg
O"tp"t.("L- =
V~~, "H"= VDO)
40
"L" : OFF of asymmeky correction.
ASYE
I
JL 80
'"H" : ON of asymmetry correction.
Name I/o Description
WDCK
I
O ] Not used
-
lnpul$ LR Clcck10 DAC (48. blt slo
O DIA mleriace. Serial data(2SCOMP
!EBE
Inputs a"dto dara to DAC.(48.br! sl
inputs bit dock to DAC.(48 -bit slot
XPCK } O
I Not used
h4NT3 I
O I Not used
MNT1 I O I NoI ,,4
yo
(
o Itd"t
! !4
.
-E
I
. . ---
w-r
I
0
Not
used
;4M
O ] Not used
EMPH o
Says "H" hx playback dwc prowd
phasis of 'L- kx that w,thoul emph
EMPHI I
De-emphasis ONK)FF of DAC. "
"L. al OFF.
WFCK
o Not used
Outputs detecvcmlor non-sound da
ZEROL
o
"H" al dekxxm Icu non+ound data
?EROR o
Outputs delec!mn for non.sound da
"H" at &tec@ for non.smmd dala
DTS1 1 Normal wed slate"L-.
AVDD3 - Power sup@yk Xlal.
XTAI I Inpuls X'L31 mlral,o" circwt (33.668
XTAO i OuIpuIs X%1 ascdlabonCtrcult(33.6
AV~~3 - GND.
AV.q-, -
GND.
IRPWM o
Outpuls PWM & R.ch. (Negabve P
?PWM O I Outputs PWM fw R.ch. (Pos,rwe P
DTS2 I Normal US.% slate "L".
I
i
Normal
used
sag
'L-.
0TS3 I
I
-58-
-59-