Table of Contents
Advertisement
IC BLOCK DIAGRAM & DESCRIPTION —
IC141 CXD2518Q ( DIGITAL SIGNAL PROCESSOR )
IC BLOCK DIAGRAM & DESCRIPTION
IC141 CXD2518Q ( DIGITAL SIGNAL PROCESSOR )
No.
Name
1/0
Description
&
41
WDCK
o
Nol used
D/A ,n,erface
(0,
48-bet s10[.
42
LRCK
o
LR clock(i=FS)
43
LRCKI
I
lnD"ls LR clock10 DAC. (48. b$l sIo1)
44
PCMD
~
O
Turns "H" when sync SO or S1 ,s oe!ec,e$
3s0
I
o ]
Seral
oulwt
of
sub-code P - V
31
ExCK
II
I
Cock ,nout for readmc SBSO.
a
I soso
I O
ISmal
o.twl of SUBO
& SOBIT
o
DIA mlerface. Scr,al da1a12'SCOMP MBS f,rst)
~
SOCK
I
Clock mpt,: for reading SOSO
45
PCMDI
1
lnpu!s add)o dala lo DAC (48.bl sIo1)
46
BCK
o
D/A interlace. B,t clock
47
BCKI
I
Inputs b,t clock to DAC. (48-blf slOt)
A9
GTOP
o
Not used
49
XUGF
o
Not used
tUPH1
LRCKI
PC"
D1
BCKI
XLAT
I
Latches input from CPU.
;0
Ser,al dala latches at falltng edge.
11
CLOK
I
Inputs serial data transfer clock from CPU.
50
XPCK
I O
Not used
1
I
1
I
Bcs
?CMD
LRCK
rDc K
12
Vss
-
I GND.
1–
13
SEIN
I
inputs SENS sgnal from SSP.
14
CNIN
I
In?uls track lump count sgnal
15
DATO
o
Outputs serial data 10 SSP
16
XLTO
o
Outputs latches to SSP.
Serial data latches a! fa!lmg edge.
77
CLKO
o
Outputs serial dala transfer clock to SSP.
18
TEST2
I
Pin for TEST. Normal used slate VDD
MUTE
C2P0
Rrcx
EEEEa
Interface for exfenson of M. Prccessor(oulPut )
Used servo auto sequencer w!th SENS outpul.
II
ERROR
/f
CORRECTOR
I
I
uNTO
U8T1
UNT3
61
DOUT
O
Not used
I
62
tMVf+
u
emphasis or 'L" !Or that Wlthoul emphasis.
63
EMPHI
I
De-emphasK
ON/OFF
01 DAC.
"H" at ON,
"L" at OFF.
64
WFCK
o
Not used
E
1--
I Stays "H" for playback disc provided
w,th I
-.
24
MON
o
ONIOFF control signal for spindle motor.
I
8rc1
tuPn
Crs
XUC1
C1OP
65 lzErl
-
Outputs delecbon for non-sound dam.
"H- at delechon for non-sound data (L.ch)
I
I
. .
l#T18f
ACC
iru
OEUODULATOR
1
I
1
II
25
MOP
o
Sewo control signal fors?mdle motor.
26
MOS
o
Not used
27
LOCK
o
Not used
.*
t
66
IZk
~,~
o
Outputs detection for non-sound dala.
"H" al deteciton for non.sound data (R-ch)
,
t
F,7
DTS ?
I
Normal
used
staie
"L".
28
TEST
I
1
I GND.
Output of f!lter for mas!er PLL.( Slave = O@al
29
FILO
o
PLL)
68
Vm
Power supply for DAC.
69
LPWM
o
Oulpuls Pwkl for L-ch. (Posbve Phase)
70
NLPWM
o
OUIP.!S PwM
forL-ch.(New.bve phase)
71
AVD02
Power
supPly for
L-ch PWM dr,ver.
72
AVD33
-
Power supply for X'(al.
73
XTAI
I
Inputs X'lal osc$llahoncmcwt (33.868 SMHZ).
74
XTAO
I
Outputs X'lal Oscdlabonctrcud (33.8688 MHz).
75
AV~~3
-
GNO.
30
FILI
1'1
Inputs to fdfer for master PLL.
I
31
Pco
o
Outputs of charge pump for mzster PLL.
32
'DD
-
Power supply for d,gj!al.f. 5V)
33
AV~~l
Power supply for analog.
34
CLTV
I
vCO control voltage mpul for master PLL.
I 'R rf=d-'l
"'"AL
I I
I==
SERVO
AUTO
SE QUt NCER
35
AV9D1
Power supply for
analo~.( +
5V)
36
RF
I
EFM s,gnal input.
37
Inpu!s
constant
current
for
asymmetry
BIAS
I
CorrectIon CIICUIL
38
Inputs comparator
voltage
for asymmetry
ASYI
I
correction clrcutt.
39
ASYO
o
EFM
{Ill swm
oumul. ["L" = V*C. "'H" = V"")
76
AV~~2
GND.
77
NRPwM
o
OuIputs PWM
forR.ch. (Negative Phase)
78
RPwM
o
Outputs PwM
forR-ch. (PosIIIve Phase)
79
0TS2
I
Normal used stale "L".
Normal used state. "L".
40
"
L" :OFF of asymmehy correction.
ASYE
1
*H" :ON ofasymmel~ correcl,
on.
II+W
'1
-61-
-60-
Hide quick links:
Advertisement
Chapters
Table of Contents
